- 04 Apr, 2024 22 commits
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Ville Syrjälä authored
No point in throwing around u8 when we're dealing with just an integer. Use a plain old boring 'int'. Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-14-ville.syrjala@linux.intel.com
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Stanislav Lisovskiy authored
Currently we can't change MBUS join status without doing a modeset, because we are lacking mechanism to synchronize those with vblank. However then this means that we can't do a fastset, if there is a need to change MBUS join state. Fix that by implementing such change. We already call correspondent check and update at pre_plane dbuf update, so the only thing left is to have a non-modeset version of that. If active pipes stay the same then fastset is possible and only MBUS join state/ddb allocation updates would be committed. The full mbus/cdclk sequence will look as follows: 1. disable pipes 2. increase cdclk if necessary 2.1 reprogram cdclk 2.2 update dbuf tracker value 3. enable mbus joining if necessary 3.1 update mbus_ctl 3.2 update dbuf tracker value 4. reallocate dbuf for planes on active pipes 5. disable mbus joining if necessary 5.1 update dbuf tracker value 5.2 update mbus_ctl 6. enable pipes 7. decrease cdclk if necessary 7.1 update dbuf tracker value 7.2 reprogram cdclk And in order to keep things in sync we need: Step 2: - mbus_join == old - mdclk/cdclk ratio == new Step 3: - mbus_join == new - mdclk/cdclk ratio == old when cdclk is changing in step 7 - mdclk/cdclk ratio == new when cdclk is changing in step 2 Step 5: - mbus_join == new - mdclk/cdclk ratio == old when cdclk is changing in step 7 - mdclk/cdclk ratio == new when cdclk is changing in step 2 Step 7: - mbus_join == new - mdclk/cdclk ratio == new v2: - Removed redundant parentheses(Ville Syrjälä) - Constified new_crtc_state in intel_mbus_joined_pipe(Ville Syrjälä) - Removed pipe_select variable(Ville Syrjälä) [v3: vsyrjala: Correctly sequence vs. cdclk updates, properly describe the full sequence, shuffle code around to make the diff more legible, streamline a few things] [v4: vsyrjala: Move the intel_cdclk_is_decreasing_later() stuff to a separate patch] Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v3 Signed-off-by:Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Co-developed-by:
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Ville Syrjälä authored
The current cdclk/mbus programming sequence is as follows: 1. intel_set_cdclk_pre_plane_update() 2. update_mbus_pre_enable() 3. intel_set_cdclk_post_plane_update() when the actual mdclk/cdclk programming is postponed to intel_set_cdclk_post_plane_update() we must keep using the old mdclk/cdclk ratio during update_mbus_pre_enable(). This guarantees the programmed ratio matches the rest of the hardware state (mdlk/cdclk/mbus joining). v2: Extracted from the vblank synchronized mbus programming patch Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1 Signed-off-by:
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Stanislav Lisovskiy authored
In order to make sure we are not breaking the proper sequence let's do updates step by step and don't change MBUS join value during MDCLK/CDCLK programming stage. MBUS join programming would be taken care by pre/post ddb hooks. v2: - Reworded comment about using old mbus_join value in intel_set_cdclk(Ville Syrjälä) Reviewed-by: -
Ville Syrjälä authored
Add some debugs so that we can actually observe what is actually happening during the mbus/dbuf programming steps. We can just shove them into fairly low level functions as none of them are called during any critical sections/etc. Reviewed-by:
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Ville Syrjälä authored
Extract the stuff that writes the dbuf/mbus ratio stuff into its own function. Will help with correctly sequencing the operations done during mbus programming. Reviewed-by:
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Ville Syrjälä authored
Extact the stuff that writes the joining bits in MBUS_CTL into its own function. Will help with correctly sequencing the operations done during mbus programming. Reviewed-by:
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Ville Syrjälä authored
intel_mbus_dbox_update() will become static soon. Relocate it into a place that avoids having to add a forward declaration for it. Reviewed-by:
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Stanislav Lisovskiy authored
We need to loop through all active pipes, not just the ones, that are in current state, because disabling and enabling even a particular pipe affects credits in another one. Reviewed-by:
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Ville Syrjälä authored
Currently we just get a plain "Changing CDCLK to ..." in the logs. It would actually be interesting to see whether we're doing the programming during the pre or post plane phase of the commit. Include that information in the debug message. Reviewed-by:
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Ville Syrjälä authored
No one ever figured out why bumping the cdclk helped with whatever issue we were having at the time. Remove the hacks and start from scratch so that we can actually see if any problems still remain. Reviewed-by:
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Ville Syrjälä authored
Currently we only consider the relationship of the old and new CDCLK frequencies when determining whether to do the repgramming from intel_set_cdclk_pre_plane_update() or intel_set_cdclk_post_plane_update(). It is technically possible to have a situation where the CDCLK frequency is decreasing, but the voltage_level is increasing due a DDI port. In this case we should bump the voltage level already in intel_set_cdclk_pre_plane_update() (so that the voltage_level will have been increased by the time the port gets enabled), while leaving the CDCLK frequency unchanged (as active planes/etc. may still depend on it). We can then reduce the CDCLK frequency to its final value from intel_set_cdclk_post_plane_update(). In order to handle that correctly we shall construct a suitable amalgam of the old and new cdclk states in intel_set_cdclk_pre_plane_update(). And we can simply call intel_set_cdclk() unconditionally in both places as it will not do anything if nothing actually changes vs. the current hw state. v2: Handle cdclk_state->disable_pipes v3: Only synchronize the cd2x update against the pipe's vblank when the cdclk frequency is changing during the current commit phase (Gustavo) Cc: stable@vger.kernel.org Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: -
Ville Syrjälä authored
Currently we always reprogram CDCLK from the intel_set_cdclk_pre_plane_update() when using squash/crawl. The code only works correctly for the cd2x update or full modeset cases, and it was simply never updated to deal with squash/crawl. If the CDCLK frequency is increasing we must reprogram it before we do anything else that might depend on the new higher frequency, and conversely we must not decrease the frequency until everything that might still depend on the old higher frequency has been dealt with. Since cdclk_state->pipe is only relevant when doing a cd2x update we can't use it to determine the correct sequence during squash/crawl. To that end introduce cdclk_state->disable_pipes which simply indicates that we must perform the update while the pipes are disable (ie. during intel_set_cdclk_pre_plane_update()). Otherwise we use the same old vs. new CDCLK frequency comparsiong as for cd2x updates. The only remaining problem case is when the voltage_level needs to increase due to a DDI port, but the CDCLK frequency is decreasing (and not all pipes are being disabled). The current approach will not bump the voltage level up until after the port has already been enabled, which is too late. But we'll take care of that case separately. v2: Don't break the "must disable pipes case" v3: Keep the on stack 'pipe' for future use Cc: stable@vger.kernel.org Fixes: d62686ba ("drm/i915/adl_p: CDCLK crawl support for ADL") Reviewed-by:
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Mitul Golani authored
Add read/write calls for Adaptive Sync SDP. Signed-off-by:
Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
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Mitul Golani authored
Compute vrr_vsync_start/end, which sets the position for hardware to send the Vsync at a fixed position relative to the end of the Vblank. --v2: - Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit) - Updated bit fields of VRR_VSYNC_START/END. (Ankit) --v3: - Add PIPE_CONF_CHECK_I(vrr.vsync_start/end). - Read/write vrr_vsync params only when we intend to send adaptive_sync sdp. --v4: - Use VRR_SYNC_START/END macros correctly. --v5: - Send AS SDP only when VRR is enabled. --v6: - Add TRANS_VRR_VSYNC before enabling VRR as per bspec. (Ankit) Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by:
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Mitul Golani authored
Enable infoframe and add state checker for Adaptive Sync SDP enablement. --v1: - crtc_state->infoframes.enable, to add on correct place holder. Signed-off-by:
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Mitul Golani authored
Add necessary function definitions to compute AS SDP data. The new intel_dp_compute_as_sdp function computes AS SDP values based on the display configuration, ensuring proper handling of Variable Refresh Rate (VRR). --v2: - Added DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx(). [Ankit] - Separated patch for intel_read/write_dp_sdp. [Ankit] - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward. [Ankit] - Fixed indentation issues. [Ankit] --v3: - Added VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. --v4: - Added HAS_VRR check before writing AS SDP. --v5: Added missed HAS_VRR check before reading AS SDP. --v6: - Used Adaptive Sync sink status as a check for read/write SDP. (Ankit) --v7: - Remove as_sdp_enable from crtc_state. - Add a comment mentioning current support of DP_AS_SDP_AVT_FIXED_VTOTAL. - Add state checker for AS_SDP infoframe enable. --v8: - Drop conn_state from intel_dp_compute_as_sdp, as not used. - Remove fullstop in subject line. --v9: - Add vrr.enable instead of is_in_vrr_range. --v10: - remove vrefresh and connector, as they are no longer required. Signed-off-by:
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Mitul Golani authored
Add a wrapper function to check if both the source and sink support Adaptive Sync SDP. --v1: Just use drm/i915/dp in subject line. Signed-off-by:
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Mitul Golani authored
Add the necessary structures and functions to handle reading and unpacking Adaptive Sync Secondary Data Packets. Also add support to write and pack AS SDP. --v2: - Correct use of REG_BIT and REG_GENMASK. [Jani] - Use as_sdp instead of async. [Jani] - Remove unrelated comments and changes. [Jani] - Correct code indent. [Jani] --v3: - Update definition names for AS SDP which are starting from HSW, as these defines are applicable for ADLP+.(Ankit) --v4: - Remove as_sdp_mode from crtc_state. - Drop metadata keyword. - For consistency, update ADL_ prefix or post fix as required. --v5: - Check if AS_SDP bit is set in crtc_state->infoframes.enable. If not return. - Check for HAS_AS_SDP() before setting VIDEO_DIP_ENABLE_AS_ADL mask. --v6: - Rename intel_read_dp_infoframe_as_sdp to intel_read_dp_as_sdp. --v7: - Add read back for length and vtotal correction. --v8: - Use as_sdp->target_rr & 0xFF. - Shift by 8 instead of 32, and drop casting to u64. - Remove changes which are does not belong to this patch. Signed-off-by:
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Mitul Golani authored
Add crtc state dump for Adaptive Sync SDP to know which crtc specifically caused the failure. --v1: - Rebase Patches to latest. Signed-off-by:
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Mitul Golani authored
Add structure representing Adaptive Sync Secondary Data Packet (AS SDP). Also, add Adaptive Sync SDP logging in drm_dp_helper.c to facilitate debugging. --v2: - Update logging. [Jani, Ankit] - Use 'as_sdp' instead of 'async' [Ankit] - Correct define placeholders to where they are actually used. [Jani] - Update members in 'as_sdp' structure to make it uniform. [Jani] --v3: - Added changes to dri-devel mailing list. No code changes. --v4: - Instead of directly using operation mode, use an enum to accommodate all operation modes (Ankit). --v5: Nit-pick changes to commit message. --v6: - Add correct place holder and name change for AS_SDP_OP_MODE. - Separate i915 changes from drm changes. - Remove extra lines. --v7: - Add drm/dp in subject line (Ankit) Signed-off-by:
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Mitul Golani authored
Add an API that indicates support for Adaptive Sync SDP in the sink, which can be utilized by the rest of the DP programming. --v1: - Format commit message properly. Signed-off-by:
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- 03 Apr, 2024 7 commits
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Ville Syrjälä authored
There is no reason to make this debugfs file for a simple boolean so complicated. Just use debugfs_create_bool(). Reviewed-by:
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Ville Syrjälä authored
ICL supposedly doesn't support FEC on MST. Reject it. Cc: stable@vger.kernel.org Fixes: d51f25eb ("drm/i915: Add DSC support to MST path") Reviewed-by:
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Ville Syrjälä authored
The MST code currently assumes that glk+ already supports MST+DSC, which is incorrect. We need to check for TGL+ actually. ICL does support SST+DSC, but supposedly it can't do MST+FEC which will also rule out MST+DSC. Note that a straight TGL+ check doesn't work here because DSC support can get fused out, so we do need to also check 'has_dsc'. Cc: stable@vger.kernel.org Fixes: d51f25eb ("drm/i915: Add DSC support to MST path") Reviewed-by:
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Ville Syrjälä authored
Simplify our life by extracting the "do we need the glk scaler clock gating w/a?" check into a small helper. Reviewed-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by:
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Ville Syrjälä authored
glk_pipe_scaler_clock_gating_wa() is messy. Clean it up via intel_de_rmw(), and also just pass in the whole crtc so the caller doesn't have to dance around so much. Reviewed-by:
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Ville Syrjälä authored
Move some of the more trivial checks in the DP .mode_valid() hooks upwards to lessen the noise amongst the more complex checks. Reviewed-by:
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Ville Syrjälä authored
We never set connector->doublescan_allowed, so the probe helper already filters out all doublescan modes for us. Sadly we still need to keep the explicit doublescan checks in .compute_config as outlined in commit e4dd27aa ("drm/i915: Allow DBLSCAN user modes with eDP/LVDS/DSI") Reviewed-by:
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- 02 Apr, 2024 9 commits
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Jani Nikula authored
This reverts commit 0d82a0d6. The commit failed to take into account that the parameter duplication and debugfs for char * parameters were subtly different between i915 core and display, and caused the DMC and PM to be disabled. Moreover, the patch was pushed with failing CI results. Revert, and get back to the drawing board. Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com>
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Rodrigo Vivi authored
Catching up on 6.9-rc2 Signed-off-by: -
Jouni Högander authored
No need to write ALPM configuration for DP2.0 Panel Replay or PSR1. Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-6-jouni.hogander@intel.com
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Jouni Högander authored
Enable ALPM AUX-Less on source side for Panel Replay eDP. Also write all calculated AUX-Less configuration values accordingly. Enabling it on sink side is in upcoming patch. Bspec: 71477 v5: - mention enable is only on source side in commit message v4: - add comment explaining why AUX less is enabled on eDP panel replay without any extra checks v3: - do not use alpm_ctl as uninitialized variable v2: - do not set AUX-Wake related bits for AUX-Less case - drop switch to active latency - add SLEEP_HOLD_TIME_50_SYMBOLS - add PORT_ALPM_CTL_MAX_PHY_SWING_HOLD Signed-off-by: -
Jouni Högander authored
Add get function for silence period and lfps half cycle. Values are taken from the tables in bspec. Bspec: 71632 v3: - use PORT_ALPM_CTL_SILENCE_PERIOD_MASK instead of value 255 - use PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK instead of value 31 v2: - fix some checks - add some more comments Signed-off-by: -
Jouni Högander authored
Calculate aux less wake time and store it into alpm_params struct Bspec: 71477 v4: - re-use fast_wake_lines to store aux_less_wake_lines v3: - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63 v2: - use variables instead of values directly - fix max value - move converting port clock to Mhz into _lnl_compute_aux_less_wake_time Signed-off-by:
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Jouni Högander authored
Couple of ALPM AUX-Less related fields are missing from ALPM register definitions. Add these and remove some duplicate definitions. Bspec: 70294 V2: add Bspec reference Signed-off-by:
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Jani Nikula authored
The dmc_firmware_path parameter is clearly a display parameter. Move it there so it's available to both i915 and xe modules. This also cleans up the ugly member in struct xe_device. Reviewed-by:
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Jani Nikula authored
Use localized __diag_push(), __diag_ignore_all() with rationale, and __diag_pop() for specific initializations instead of blanket disabling of -Woverride-init across several files. Note that we've tried this before with commit 88e96644 ("drm/i915: use localized __diag_ignore_all() instead of per file") and reverted in commit 290d1610 ("Revert "drm/i915: use localized __diag_ignore_all() instead of per file""). The issue turned out to be in __diag_ignore_all() and it was fixed by commit 689b097a ("compiler-gcc: Suppress -Wmissing-prototypes warning for all supported GCC"). So we should be able to pull this off now. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
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- 01 Apr, 2024 1 commit
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Ankit Nautiyal authored
For DISPLAY < 13, compressed bpp is chosen from a list of supported compressed bpps. Fix the condition to choose the appropriate compressed bpp from the list. Fixes: 1c56e9a3 ("drm/i915/dp: Get optimal link config to have best compressed bpp") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: <stable@vger.kernel.org> # v6.7+ Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10162Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240305054443.2489895-1-ankit.k.nautiyal@intel.com
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- 31 Mar, 2024 1 commit
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Linus Torvalds authored
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