- 28 Jan, 2008 40 commits
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Paul Mundt authored
Signed-off-by:Paul Mundt <lethal@linux-sh.org>
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Paul Mundt authored
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Paul Mundt authored
This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: -
Stuart Menefy authored
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Stuart Menefy <stuart.menefy@st.com> Signed-off-by:
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Thomas Betker authored
This patch changes the uImage target so that it generates a wrapped compressed vmlinux, rather than a wrapped zImage. The previous version matched the ARM, this version matches the PPC. However I would question how useful a self decompressing image is with a boot loader which does decompression, so I think this is more useful. I also feel it matches the descrition in the help text ("Compressed kernel image") better. Signed-off-by:Thomas Betker <thomas.betker@5etech.eu> Signed-off-by:
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Stuart Menefy authored
When a get_user(to, from++) is called the pointer increment is performed after its first usage, in the specific after the __add_ok invokation. This causes a wrong get_user return value, putting a wrong character in the destination variable. This patch solves the problem using a new temporary pointer. Additionally this reworks the use of the register banks, allowing for consolidation between the MMU and nommu implementations. Signed-off-by:
Carmelo Amoroso <carmelo.amoroso@st.com> Signed-off-by:
Giuseppe Condorelli <giuseppe.condorelli@st.com> Signed-off-by:
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Stuart Menefy authored
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Stuart Menefy authored
This saves us from having to use kmalloc() for the fixmap entries, which is needed early for the uncached fixmap. Signed-off-by:
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Stuart Menefy authored
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Stuart Menefy authored
Presently most of the 29-bit physical parts do P1/P2 segmentation with a 1:1 cached/uncached mapping, jumping between the two to control the caching behaviour. This provides the basic infrastructure to maintain this behaviour on 32-bit physical parts that don't map P1/P2 at all, using a shiny new linker section and corresponding fixmap entry. Signed-off-by:
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Paul Mundt authored
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Stuart Menefy authored
This implements kernel-level atomic rollback built on top of gUSA, as an alternative non-IRQ based atomicity method. This is generally a faster method for platforms that are lacking the LL/SC pairs that SH-4A and later use, and is only supportable on legacy cores. Signed-off-by:
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Nobuhiro Iwamatsu authored
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Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by:
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Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
With all of the different CPU types this was getting a but unwieldly. Since sh64 is now integrated, we don't have to worry about multiple architectures caring about the header definitions. Split out the defs for each asm/cpu/ to make rtc-sh slightly less visually offensive. Signed-off-by: -
Paul Mundt authored
Avoid namespace collision with a CCR1 definition. The general SH code always expects CCR anyways, so there's no point in keeping the CCR1 naming around. Fixes up synclink collisions: drivers/char/pcmcia/synclink_cs.c:283:1: warning: "CCR1" redefined In file included from include/asm/cache.h:13, from include/asm/processor_32.h:15, from include/asm/processor.h:60, from include/linux/prefetch.h:14, from include/linux/list.h:8, from include/linux/module.h:9, from drivers/char/pcmcia/synclink_cs.c:38: include/asm/cpu/cache.h:21:1: warning: this is the location of the previous definition Reported-by:Andrew Morton <akpm@linux-foundation.org> Signed-off-by:
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Paul Mundt authored
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Stuart Menefy authored
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Stuart Menefy authored
Shoves a magic word in to the empty_zero_page section for the bootloader to work out whether to start the kernel in 29-bit or 32-bit mode. [ Renesas CPUs already take care of the initial PMB mappings entirely in hardware and decide on 29-bit/32-bit physical depending on which pin powered up the CPU, so this is mostly for ST parts. -- PFM ]. Signed-off-by:
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Stuart Menefy authored
mem= can't be used to grow the size of kernel memory, so provide a warning to that effect. Signed-off-by:
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Paul Mundt authored
Signed-off-by:
Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by:
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Paul Mundt authored
This adds support for the SH7263 (SH-2A) CPU. This particular CPU is a superset of SH7203, adding some additional peripheral blocks and hooking up additional (reserved on SH7203) vectors in the INTC block. No visibly nasty surprises, yet.. Signed-off-by: -
Paul Mundt authored
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Paul Mundt authored
This adds support for the SH7203 (SH-2A) CPU. Signed-off-by:
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Paul Mundt authored
Trivial support for the SH-2A on-chip RTC. Signed-off-by: -
Yuichi Nakamura authored
Support syscall auditing.. Signed-off-by:
Yuichi Nakamura <ynakam@hitachisoft.jp> Signed-off-by:
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Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
This was using the absolute path, which was confusing the make target. Switch it to just 'zImage', as per powerpc. Signed-off-by: -
Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
Sync up with the SH definitions. Signed-off-by: -
Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
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Paul Mundt authored
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