- 21 Jun, 2015 40 commits
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Paul Gortmaker authored
We removed __cpuinit support (leaving no-op stubs) quite some time ago. However a new instance was added in commit 4caa906e ("MIPS: mm: c-r4k: Build EVA {d,i}cache flushing functions") Since we want to clobber the stubs soon, get this removed now. Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9893/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Gortmaker authored
We removed __cpuinit support (leaving no-op stubs) quite some time ago. However a few more crept in as of commit 6ee1d934 ("MIPS: BCM47XX: Detect more then 128 MiB of RAM (HIGHMEM)") Since we want to clobber the stubs soon, get this removed now. Signed-off-by:
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Paul Gortmaker authored
We removed __cpuinit support (leaving no-op stubs) quite some time ago. However this one crept back in as of commit 43cc739f ("MIPS: ath25: add common parts") Since we want to clobber the stubs soon, get this removed now. Signed-off-by:
Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9891/Signed-off-by:
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Andrew Bresticker authored
Update pistachio_defconfig to enable Pistachio's USB PHY driver. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hartley <james.hartley@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9729/Signed-off-by:
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Andrew Bresticker authored
Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by:
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Andrew Bresticker authored
Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC. Signed-off-by:
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Ezequiel Garcia authored
Pistachio SoCs are capable of early printk with generic 8250 support, so let's select the options to enable it. Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9913/Signed-off-by:
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Jaedon Shin authored
Add two uart device nodes known as the uart1 and uart2 for the bcm7xxx platforms. Signed-off-by:
Jaedon Shin <jaedon.shin@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9991/Signed-off-by:
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Florian Fainelli authored
Add a DTS file and Kconfig entry for the BCM97435SVMB evaluation board using bcm7435.dtsi as an example. The current code needs some tweaking to allow us to use the dual-threaded dual BMIPS5200 CPUs, so for now we limit ourselves to allowing just a single CPU to be booted. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: blogic@openwrt.org Cc: cernekee@chromium.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/9972/Signed-off-by:
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Florian Fainelli authored
Add the bare minimum required to boot a BCM7435-based system: - BMIPS5200 CPU nodes - Level 1 and 2 interrupt controllers - UARTs - EHCI/OHCI controllers Signed-off-by:
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Florian Fainelli authored
Since BCM63xx runs on BMIPS3300 which requires the use of a FIXADDR_TOP to avoid collisions with the SBR, utilize asm/bmips-spaces.h which defines FIXADDR_TOP for us now. Signed-off-by:
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Florian Fainelli authored
The FIXADDR_TOP value used by mach-bmips is in fact required whenever we run on BMIPS3300 BMIPS CPUs, and is not machine, but CPU-specific, move this constant to asm/bmips-spaces.h and use it in mach-bmips/spaces.h. Signed-off-by:
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Rafał Miłecki authored
Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: Arend van Spriel <arend@broadcom.com> Patchwork: https://patchwork.linux-mips.org/patch/10207/Signed-off-by:
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Paul Burton authored
Add an initial device tree for the Ingenic JZ4780 based MIPS Creator CI20 board. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10162/Signed-off-by:
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Paul Burton authored
Support the Ingenic JZ4780 SoC using the existing code under arch/mips/jz4740 now that it has been generalised sufficiently. Signed-off-by:
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Paul Burton authored
Remove the serial support from arch/mips/jz4740 & make use of the new Ingenic SoC UART driver. This is done for both regular & early console output. Signed-off-by:
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Paul Burton authored
Introduce a driver suitable for use with the UARTs present in Ingenic SoCs such as the JZ4740 & JZ4780. These are described as being ns16550 compatible but aren't quite - they require the setting of an extra bit in the FCR register to enable the UART module. The serial_out implementation is the same as that in arch/mips/jz4740/serial.c - which will shortly be removed. Signed-off-by:
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Paul Burton authored
Add binding documentation for the UARTs found in Ingenic SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10161/Signed-off-by:
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Paul Burton authored
Allow a devicetree to specify the memory present in the system rather than probing it from the memory controller. This both saves the probing for systems where the amount of memory is fixed, and will simplify the bringup of later Ingenic SoCs where the memory controller register layout differs. Signed-off-by:
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Paul Burton authored
The only thing remaining in arch/mips/jz4740/clock.h is declarations of the jz4740_clock_{suspend,resume} functions. Move these to arch/mips/include/asm/mach-jz4740/clock.h for consistency with similar functions, and remove the redundant arch/mips/jz4740/clock.h header. Signed-off-by: -
Paul Burton authored
Add support for the clocks provided by the CGU in the Ingenic JZ4780 SoC, making use of the SoC-agnostic CGU code to do the heavy lifting. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10157/Signed-off-by:
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Paul Burton authored
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_{suspend,resume} functions there for such consistency. The arch/mips/jz4740/clock.c file now contains nothing more of use & so is removed. Signed-off-by: -
Paul Burton authored
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move the jz4740_clock_udc_{dis,en}able_auto_suspend functions there for such consistency. Signed-off-by: -
Paul Burton authored
The jz4740-cgu driver already has access to the CGU, so it makes sense to move the few remaining accesses to the CGU from arch/mips/jz4740 there too. Move jz4740_clock_set_wait_mode for such consistency. Signed-off-by:
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Paul Burton authored
Migrate the JZ4740 & the qi_lb60 board to use common clock framework via the new Ingenic SoC CGU driver. Note that the JZ4740-specific debugfs code is removed since common clock framework provides its own debug capabilities. Signed-off-by:
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Paul Burton authored
This driver supports the CGU clocks for Ingenic SoCs. It is generic enough to be usable across at least the JZ4740 to the JZ4780, and will be made use of on such devices in subsequent commits. This patch by itself only adds the SoC-agnostic infrastructure that forms the bulk of the CGU driver for the aforementioned further commits to make use of. Signed-off-by:
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Paul Burton authored
Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 & JZ4780 CGU blocks. Signed-off-by:
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Paul Burton authored
Replace uses of the jz4740_clock_bdata struct with calls to clk_get_rate for the appropriate clock. This is in preparation for migrating the clocks towards common clock framework & devicetree. Signed-off-by:
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Paul Burton authored
Call jz4740_clock_init before any uses of jz4740_clock_bdata occur. This is in preparation for replacing uses of that struct with calls to clk_get_rate, which will allow the clocks to be migrated towards common clock framework & devicetree. Signed-off-by:
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Paul Burton authored
Move the driver for Ingenic SoC interrupt controllers into drivers/irqchip where it belongs. Signed-off-by:
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Paul Burton authored
Allow the interrupt controllers of the JZ4770, JZ4775 & JZ4780 SoCs to be probed via devicetree, supporting the 64 interrupts they provide. Signed-off-by:
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Paul Burton authored
Rename the functions including jz4740 in their names to be more generic in preparation for supporting further SoCs, and for moving this interrupt controller code to drivers/irqchip. Signed-off-by:
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Paul Burton authored
Read the base address of the SoC interrupt controller from the device tree rather than relying upon the JZ4740_INTC_BASE_ADDR macro, in order to remove the dependency on the asm/mach-jz4740/base.h header. Signed-off-by:
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Paul Burton authored
For interrupts numbered after those of the interrupt controller, define their numbers based upon the number of interrupts provided by the SoC interrupt controller. This is in preparation for supporting newer Ingenic SoCs which provide more interrupts. Signed-off-by:
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Paul Burton authored
On newer Ingenic SoCs the interrupt controller supports more than 32 interrupts, which it does by duplicating the registers at intervals of 0x20 bytes within its address space. Add support for an arbitrary number of interrupts using multiple generic chips, and provide the number of chips to register from the interrupt controller probe function. Signed-off-by:
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Paul Burton authored
Avoid the need for the global variable jz_intc_base by introducing a struct ingenic_intc_data and passing it around as the IRQ handler data. Signed-off-by:
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Paul Burton authored
The debugfs code becomes a nuisance when attempting to avoid globals, since the interrupt controller probe function run too early for it to be safe to create the debugfs files. Drop it. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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Paul Burton authored
When probing the interrupt controller, register an IRQ domain such that the interrupts can be translated by devicetree code & thus used from devicetree. Signed-off-by:
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Paul Burton authored
Rather than hardcoding the IRQ number used to cascade interrupts from the SoC interrupt controller to the CPU interrupt controller, read that IRQ number from the DT describing the system. Signed-off-by:
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Paul Burton authored
Declare the JZ4740 interrupt controller for probe via DT using the standard irqchip_init function, and make use of that function to probe the controller by adding the appropriate node to the JZ4740 dtsi. Signed-off-by:
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