- 07 Mar, 2023 20 commits
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Hawking Zhang authored
Add PSP IP handling for PSP 13.0.6 Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Le Ma <Le.Ma@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Initialize ta ucode for psp v13_0_6 Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Hawking Zhang authored
parse psp_v13_0_6_sos.bin and initialze various psp ucode arraies respectively Signed-off-by:
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Hawking Zhang authored
Initialize psp ip callbacks for PSP 13.0.6. Signed-off-by:
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Le Ma authored
Use sdma 4.4.2 IP block for chips with sdma 4.4.2 hardware. Signed-off-by:
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Le Ma authored
Add support for SDMA 4.4.2. v1: Create sdma_v4_4_2.[c|h] for initial support (Le) v2: update amdgpu_ring_init call with atomic score (Hawking) v3: Squash in sdma_start fixes (Alex) v4: Comment out currently unused RAS code (Alex) Signed-off-by:
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Hawking Zhang authored
Add sdma v4_4_2 register offset and shift masks header files v2: update headers (Alex) Signed-off-by:
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Hawking Zhang authored
Add HDP IP handling for HDP 4.4.2 Signed-off-by:
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Le Ma authored
No mmHDP_READ_CACHE_INVALIDATE register on HDP 4.4.2. Signed-off-by:
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Hawking Zhang authored
Add hdp v4_4_2 register offset and shift masks header files v2: update headers (Alex) Signed-off-by:
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Hawking Zhang authored
Add IH IP handling for IH 4.4.2 Signed-off-by:
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Le Ma authored
No ih2 hardware on IH 4.4.2. Signed-off-by:
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Le Ma authored
Share same register address with IH 4.4.0. Signed-off-by:
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Muhammad Usama Anjum authored
The less than zero comparison of unsigned variable "value" is never true. Remove dead code. Fixes: c3ed0e72 ("drm/amdgpu: added a sysfs interface for thermal throttling") Signed-off-by:
Muhammad Usama Anjum <usama.anjum@collabora.com> Signed-off-by:
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Deepak R Varma authored
The if / else block code has same effect irrespective of the logical evaluation. Hence, simply the implementation by removing the unnecessary conditional evaluation. While at it, also fix the long line checkpatch complaint. Issue identified using cond_no_effect.cocci Coccinelle semantic patch script. Fixes: 9114b55f ("drm/amd/display: Fix SubVP control flow in the MPO context") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Deepak R Varma <drv@mailo.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Daniel Phillips authored
Our assumptions about how much KFD memory is currently available for allocation may be violated by various complexities so we define the reported value as advisory, however we should never report negative availability. Signed-off-by:
Daniel Phillips <daniel.phillips@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Mario Limonciello authored
The same strapping initialization issue that happened on NBIO 7.5.1 appears to be happening on NBIO 7.3.0. Apply the same fix to 7.3.0 as well. Note: This workaround relies upon the integrated GPU being enabled in BIOS. If the integrated GPU is disabled in BIOS a different workaround will be required. Reported-by:
Thomas Glanzmann <thomas@glanzmann.de> Cc: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@glanzmann.de/T/#uSigned-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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lyndonli authored
On GPUs with RAS enabled, below call trace and hang are observed when shutting down device. v2: use DRM device unplugged flag instead of shutdown flag as the check to prevent memory wipe in shutdown stage. [ +0.000000] RIP: 0010:amdgpu_vram_mgr_fini+0x18d/0x1c0 [amdgpu] [ +0.000001] PKRU: 55555554 [ +0.000001] Call Trace: [ +0.000001] <TASK> [ +0.000002] amdgpu_ttm_fini+0x140/0x1c0 [amdgpu] [ +0.000183] amdgpu_bo_fini+0x27/0xa0 [amdgpu] [ +0.000184] gmc_v11_0_sw_fini+0x2b/0x40 [amdgpu] [ +0.000163] amdgpu_device_fini_sw+0xb6/0x510 [amdgpu] [ +0.000152] amdgpu_driver_release_kms+0x16/0x30 [amdgpu] [ +0.000090] drm_dev_release+0x28/0x50 [drm] [ +0.000016] devm_drm_dev_init_release+0x38/0x60 [drm] [ +0.000011] devm_action_release+0x15/0x20 [ +0.000003] release_nodes+0x40/0xc0 [ +0.000001] devres_release_all+0x9e/0xe0 [ +0.000001] device_unbind_cleanup+0x12/0x80 [ +0.000003] device_release_driver_internal+0xff/0x160 [ +0.000001] driver_detach+0x4a/0x90 [ +0.000001] bus_remove_driver+0x6c/0xf0 [ +0.000001] driver_unregister+0x31/0x50 [ +0.000001] pci_unregister_driver+0x40/0x90 [ +0.000003] amdgpu_exit+0x15/0x120 [amdgpu] Signed-off-by:
lyndonli <Lyndon.Li@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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bobzhou authored
building with gcc and W=1 reports drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c:7292:11: error: unused variable 'tmp' [-Werror=unused-variable] uint32_t tmp; ^~~ tmp is not used so remove it. Signed-off-by:bobzhou <bob.zhou@amd.com> Reviewed-by:
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Xiaogang Chen authored
svm_migrate_ram_to_vram migrates a prange from sys ram to vram. The prange may cross multiple vma. Need remember current dst vram offset in the TTM resource for each migration. v2: squash in warning fix (Alex) Signed-off-by:
Xiaogang Chen <Xiaogang.Chen@amd.com> Reviewed-by:
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- 06 Mar, 2023 8 commits
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Swapnil Patel authored
[Why] Currently, the clk manager matches SocVoltage with voltage from fused settings (dfPstate clock table). And then corresponding clocks are selected. However in certain situations, this leads to clk manager not including at least one entry with highest supported clock setting. [How] Update the clk manager to include at least one entry with highest supported clock setting. Reviewed-by:
Pavle Kotarac <pavle.kotarac@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Swapnil Patel <Swapnil.Patel@amd.com> Signed-off-by:
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Christian König authored
We have a wait in the amdgpu_bo_kmap() code for quite a while now, so waiting here isn't needed any more. Signed-off-by:
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Candice Li authored
Support EccInfoTable which includes umc ras error count and error address. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
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Candice Li authored
Don't need to query error count and error address on harvest umc nodes. v2: Fix code bug, use active_mask instead of harvsest_config and remove unnecessary argument in LOOP macro. v3: Leave adev->gmc.num_umc unchanged. Signed-off-by:Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Kun Liu authored
add static prefix for vangogh_set_apu_thermal_limit function Signed-off-by:
Kun Liu <Kun.Liu2@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/oe-kbuild-all/202303010827.c2N0yBGT-lkp@intel.comReviewed-by:
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leiyaoyao authored
Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform IDLE-SAVE after VF fini. Otherwise it could cause GFX hang if another Win guest is rendering. Signed-off-by:
leiyaoyao <yaoyao.lei@amd.com> Acked-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
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Harry Wentland authored
This is useful to understand the bpc defaults and support of a driver. Signed-off-by:
Joshua Ashton <joshua@froggi.es> Link: https://patchwork.freedesktop.org/patch/msgid/20230113162428.33874-3-harry.wentland@amd.comSigned-off-by:
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Harry Wentland authored
The EDID of an HDR display defines EOTFs that are supported by the display and can be set in the HDR metadata infoframe. Userspace is expected to read the EDID and set an appropriate HDR_OUTPUT_METADATA. In drm_parse_hdr_metadata_block the kernel reads the supported EOTFs from the EDID and stores them in the drm_connector->hdr_sink_metadata. While doing so it also filters the EOTFs to the EOTFs the kernel knows about. When an HDR_OUTPUT_METADATA is set it then checks to make sure the EOTF is a supported EOTF. In cases where the kernel doesn't know about a new EOTF this check will fail, even if the EDID advertises support. Since it is expected that userspace reads the EDID to understand what the display supports it doesn't make sense for DRM to block an HDR_OUTPUT_METADATA if it contains an EOTF the kernel doesn't understand. This comes with the added benefit of future-proofing metadata support. If the spec defines a new EOTF there is no need to update DRM and an compositor can immediately make use of it. Bug: https://gitlab.freedesktop.org/wayland/weston/-/issues/609 v2: Distinguish EOTFs defind in kernel and ones defined in EDID in the commit description (Pekka) v3: Rebase; drm_hdmi_infoframe_set_hdr_metadata moved to drm_hdmi_helper.c Signed-off-by:
Pekka Paalanen <pekka.paalanen@collabora.com> Reviewed-By:
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- 28 Feb, 2023 12 commits
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Aric Cyr authored
This version brings along the following: - Correct DML calculation - Extend Freesync over Pcon support - Fixes in pstate hang and more - Code cleanup for dc_link.h and dc_link.c Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] The newer commit sequence on DCN32 onwards did not finish clock optimization sequence since the newer sequence did not end up calling dc_post_update_surfaces_to_stream() which resets dc->optimized_required. Call this function before passing control on to the new commit sequence. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Aric Cyr authored
[why] While bandwidth optimizations are pending, it's possible a pstate change will occur. During this time, VSYNC handler should not also try to update DRR parameters causing pstate hang [how] Do not adjust DRR if optimize bandwidth is set. Reviewed-by:
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Aric Cyr authored
[why] If OTG is not active, waiting for blank completion will always fail and timeout resulting in unnecessary driver delays. [how] Check that OTG is enabled before waiting for blank. Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Samson Tam authored
[Why] In disable_dangling_plane, for phantom pipes, we enable OTG so disable programming gets the double buffer update. But this causes an underflow to occur. [How] Enable DPG prior to enabling OTG. Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Wenjing Liu authored
[why] We kept an empty dc_link.c file due to external build dependency. Now the last build dependency has been removed. We can safely delete this file. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Paul Hsieh authored
[Why] In 2560x1440@240p eDP panel, some use cases will enable MPC combine with RGB MPO then underflow happened. This case is not allowed from HW formula. [How] Correct eDP, DP and DP2 output bpp calculation to align HW formula. Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Paul Hsieh <Paul.Hsieh@amd.com> Tested-by:
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bobzhou authored
This patch is used to fix following compilation issue with legacy gcc error: ‘for’ loop initial declarations are only allowed in C99 mode for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) { Signed-off-by: -
Felix Kuehling authored
Exports a DMA buf fd of a given KFD buffer handle. This is intended for being able to import KFD BOs into GEM contexts to leverage the amdgpu_bo_va API for more flexible virtual address mappings. It will also be used for the new upstreamable RDMA solution coming to UCX and RCCL. The corresponding user mode change (Thunk API and kfdtest) is here: https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabufSigned-off-by:
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Felix Kuehling authored
Use proper amdgpu_gem_prime_import function to handle all kinds of imports. Remember the dmabuf reference to enable proper multi-GPU attachment to multiple VMs without erroneously re-exporting the underlying BO multiple times. Signed-off-by:
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Wenjing Liu authored
[why] Remove the need to include dc_link.h separately. dc.h should contain everything needed on DM side. [How] Merge dc_link.h into dc.h and dc_types.h so DM only needs to include dc.h to use all link public functions. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Mustapha Ghaddar authored
[WHY & HOW] Update the declaration to give a better idea of what the function does. Reviewed-by:
Mustapha Ghaddar <mghaddar@amd.com> Tested-by:
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