- 16 Aug, 2023 3 commits
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Drew Fustini authored
Modify the SPDX-License-Identifier for dual license of GPL-2.0 OR MIT. Signed-off-by:
Drew Fustini <dfustini@baylibre.com> Acked-by:
Jisheng Zhang <jszhang@kernel.org> Acked-by:
Guo Ren <guoren@kernel.org> Reviewed-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Drew Fustini authored
The BeagleV Ahead single board computer uses the T-Head TH1520 SoC. Add a minimal device tree to support basic uart/gpio/dmac drivers so that a user can boot to a basic shell. Link: https://beagleboard.org/beaglev-aheadReviewed-by:
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Drew Fustini authored
Document the compatible strings for the BeagleV Ahead board which uses the T-Head TH1520 SoC. Link: https://beagleboard.org/beaglev-aheadAcked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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- 15 Aug, 2023 1 commit
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Conor Dooley authored
Emil pointed out that "13010000 sorts after 12070000". Reshuffle the entries to be in-order. Reported-by:
Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by:
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- 13 Aug, 2023 1 commit
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Samin Guo authored
Fixed configuration to improve the speed of TCP RX. Before: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47604 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47612 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 36.3 MBytes 305 Mbits/sec [ 5] 1.00-2.00 sec 35.6 MBytes 299 Mbits/sec [ 5] 2.00-3.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 3.00-4.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 4.00-5.00 sec 35.7 MBytes 300 Mbits/sec [ 5] 5.00-6.00 sec 35.4 MBytes 297 Mbits/sec [ 5] 6.00-7.00 sec 37.1 MBytes 311 Mbits/sec [ 5] 7.00-8.00 sec 35.6 MBytes 298 Mbits/sec [ 5] 8.00-9.00 sec 36.4 MBytes 305 Mbits/sec [ 5] 9.00-10.00 sec 36.3 MBytes 304 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 361 MBytes 303 Mbits/sec receiver After: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47710 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47720 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 111 MBytes 932 Mbits/sec [ 5] 1.00-2.00 sec 111 MBytes 934 Mbits/sec [ 5] 2.00-3.00 sec 111 MBytes 934 Mbits/sec [ 5] 3.00-4.00 sec 111 MBytes 934 Mbits/sec [ 5] 4.00-5.00 sec 111 MBytes 934 Mbits/sec [ 5] 5.00-6.00 sec 111 MBytes 935 Mbits/sec [ 5] 6.00-7.00 sec 111 MBytes 934 Mbits/sec [ 5] 7.00-8.00 sec 111 MBytes 935 Mbits/sec [ 5] 8.00-9.00 sec 111 MBytes 934 Mbits/sec [ 5] 9.00-10.00 sec 111 MBytes 934 Mbits/sec [ 5] 10.00-10.00 sec 167 KBytes 933 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 1.09 GBytes 934 Mbits/sec receiver Reviewed-by:
Hal Feng <hal.feng@starfivetech.com> Signed-off-by:
Samin Guo <samin.guo@starfivetech.com> Fixes: 1ff166c9 ("riscv: dts: starfive: jh7110: Add ethernet device nodes") Reviewed-by:
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- 09 Aug, 2023 4 commits
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Jia Jie Ho authored
Add hardware rng controller node for StarFive JH7110 SoC. Co-developed-by:
Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by:
Jia Jie Ho <jiajie.ho@starfivetech.com> Acked-by:
Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by:
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Jia Jie Ho authored
Add hardware crypto module and dedicated dma controller node to StarFive JH7110 SoC. Co-developed-by:
Huan Feng <huan.feng@starfivetech.com> Signed-off-by:
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William Qiu authored
Add the mmc nodes for the StarFive JH7110 SoC. Set mmc0 node to emmc and set mmc1 node to sd. Signed-off-by:
William Qiu <william.qiu@starfivetech.com> Reviewed-by:
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William Qiu authored
Enable DCDC1 node for vmmc-supply and enable ALDO4 node for vqmmc-supply. Signed-off-by:
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- 05 Aug, 2023 1 commit
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William Qiu authored
Add the quad spi controller node for the StarFive JH7110 SoC. Co-developed-by:
Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by:
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- 26 Jul, 2023 5 commits
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Walker Chen authored
Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Reviewed-by:
Walker Chen <walker.chen@starfivetech.com> Signed-off-by:
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Walker Chen authored
Add the dma controller node for the Starfive JH7110 SoC. Reviewed-by:
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William Qiu authored
Add StarFive JH7110 SPI controller node and pins configuration on VisionFive 2 board. Signed-off-by:
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Minda Chen authored
Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. Signed-off-by:
Minda Chen <minda.chen@starfivetech.com> Signed-off-by:
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Minda Chen authored
Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC. Signed-off-by:
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- 25 Jul, 2023 3 commits
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Hal Feng authored
Add temperature sensor and thermal-zones support for the StarFive JH7110 SoC. CPUFreq cooling is supported in thermal-zones. Co-developed-by:
Emil Renner Berthing <kernel@esmil.dk> Signed-off-by:
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Hal Feng authored
Add temperature sensor and thermal-zones support for the StarFive JH7100 SoC. Co-developed-by:
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Samin Guo authored
v1.3B: v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and inverse configurations. The tx_clk of v1.3B uses an external clock and needs to be switched to an external clock source. v1.2A: v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay configurations. v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and rx to external clock sources. Tested-by:
Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by:
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- 20 Jul, 2023 6 commits
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Samin Guo authored
Add JH7110 ethernet device node to support gmac driver for the JH7110 RISC-V SoC. Tested-by:
Yanhong Wang <yanhong.wang@starfivetech.com> Signed-off-by:
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Xingyu Wu authored
Add PLL clocks input from PLL clocks driver in SYSCRG node. Reviewed-by:
Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by:
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William Qiu authored
Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC. Reviewed-by:
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Xingyu Wu authored
Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 System-Top-Group, Image-Signal-Process and Video-Output clock and reset drivers for the JH7110 RISC-V SoC. Acked-by:
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Xingyu Wu authored
Add DVP and HDMI TX pixel external fixed clocks and the rates are 74.25MHz and 297MHz. Acked-by:
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Conor Dooley authored
This is the dt-binding base for the new starfive clock stuff, that has been merged into the clk tree by Stephen. Signed-off-by:
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- 19 Jul, 2023 6 commits
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Xingyu Wu authored
Add bindings for the Video-Output clock and reset generator (VOUTCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by:
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Xingyu Wu authored
Add bindings for the Image-Signal-Process clock and reset generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by:
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Xingyu Wu authored
Add bindings for the System-Top-Group clock and reset generator (STGCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by:
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Xingyu Wu authored
Add PLL clock inputs from PLL clock generator. Reviewed-by:
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William Qiu authored
Add documentation to describe StarFive System Controller Registers. Reviewed-by:
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Xingyu Wu authored
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by:
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- 12 Jul, 2023 1 commit
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Felix Moessbauer authored
Add the '-@' DTC option for the starfive devices. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (for instance from the firmware or the bootloader) on these devices. The starfive devices allow various modules to be connected and this enables users to create out-of-tree device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB by ~20%. For example, with v6.4 increase in size is as follows: jh7100-beaglev-starlight.dtb 6192 -> 7339 jh7100-starfive-visionfive-v1.dtb 6281 -> 7428 jh7110-starfive-visionfive-2-v1.2a.dtb 11101 -> 13447 jh7110-starfive-visionfive-2-v1.3b.dtb 11101 -> 13447 Signed-off-by:
Felix Moessbauer <felix.moessbauer@siemens.com> Acked-by:
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- 09 Jul, 2023 9 commits
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Linus Torvalds authored
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Linus Torvalds authored
We just sorted the entries and fields last release, so just out of a perverse sense of curiosity, I decided to see if we can keep things ordered for even just one release. The answer is "No. No we cannot". I suggest that all kernel developers will need weekly training sessions, involving a lot of Big Bird and Sesame Street. And at the yearly maintainer summit, we will all sing the alphabet song together. I doubt I will keep doing this. At some point "perverse sense of curiosity" turns into just a cold dark place filled with sadness and despair. Repeats: 80e62bc8 ("MAINTAINERS: re-sort all entries and fields") Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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git://git.infradead.org/users/hch/dma-mappingLinus Torvalds authored
Pull dma-mapping fixes from Christoph Hellwig: - swiotlb area sizing fixes (Petr Tesarik) * tag 'dma-mapping-6.5-2023-07-09' of git://git.infradead.org/users/hch/dma-mapping: swiotlb: reduce the number of areas to match actual memory pool size swiotlb: always set the number of areas before allocating the pool
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull irq update from Borislav Petkov: - Optimize IRQ domain's name assignment * tag 'irq_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqdomain: Use return value of strreplace()
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fpu fix from Borislav Petkov: - Do FPU AP initialization on Xen PV too which got missed by the recent boot reordering work * tag 'x86_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/xen: Fix secondary processors' FPU initialization
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fix from Thomas Gleixner: "A single fix for the mechanism to park CPUs with an INIT IPI. On shutdown or kexec, the kernel tries to park the non-boot CPUs with an INIT IPI. But the same code path is also used by the crash utility. If the CPU which panics is not the boot CPU then it sends an INIT IPI to the boot CPU which resets the machine. Prevent this by validating that the CPU which runs the stop mechanism is the boot CPU. If not, leave the other CPUs in HLT" * tag 'x86-core-2023-07-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/smp: Don't send INIT to boot CPU
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git://git.kernel.org/pub/scm/linux/kernel/git/mips/linuxLinus Torvalds authored
Pull MIPS fixes from Thomas Bogendoerfer: - fixes for KVM - fix for loongson build and cpu probing - DT fixes * tag 'mips_6.5_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: kvm: Fix build error with KVM_MIPS_DEBUG_COP0_COUNTERS enabled MIPS: dts: add missing space before { MIPS: Loongson: Fix build error when make modules_install MIPS: KVM: Fix NULL pointer dereference MIPS: Loongson: Fix cpu_probe_loongson() again
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git://git.kernel.org/pub/scm/fs/xfs/xfs-linuxLinus Torvalds authored
Pull xfs fix from Darrick Wong: "Nothing exciting here, just getting rid of a gcc warning that I got tired of seeing when I turn on gcov" * tag 'xfs-6.5-merge-6' of git://git.kernel.org/pub/scm/fs/xfs/xfs-linux: xfs: fix uninit warning in xfs_growfs_data
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git://git.samba.org/sfrench/cifs-2.6Linus Torvalds authored
Pull more smb client updates from Steve French: - fix potential use after free in unmount - minor cleanup - add worker to cleanup stale directory leases * tag '6.5-rc-smb3-client-fixes-part2' of git://git.samba.org/sfrench/cifs-2.6: cifs: Add a laundromat thread for cached directories smb: client: remove redundant pointer 'server' cifs: fix session state transition to avoid use-after-free issue
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