- 14 Sep, 2021 14 commits
-
-
xinhui pan authored
Direct IB pool is used for vce/vcn IB extra msg too. Increase its size to AMDGPU_IB_POOL_SIZE. v2: Squash in unused variable removal Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Lang Yu authored
Add manual sclk/vddc setting supoort via pp_od_clk_voltage sysfs to maintain consistency with other asics. As cyan skillfish doesn't support DPM, there is only a single frequency and voltage to adjust. v2: maintain consistency and add command guide. v3: adjust user settings storage and coding style. Command guide: echo vc point sclk vddc > pp_od_clk_voltage "vc" - sclk voltage curve "point" - must be 0 "sclk" - target value of sclk(MHz), should be in safe range "vddc" - target value of vddc(mV), a 6.25(mV) stepping is recommended and should be in safe range (the real vddc is an approximation of target value) echo c > pp_od_clk_voltage "c" - commit the changes of sclk and vddc, only after the commit command, the target values set by "vc" command will take effect echo r > pp_od_clk_voltage "r" - reset sclk and vddc to default value, a subsequent commit command is needed to take effect Example: 1) Check default sclk and vddc $ cat pp_od_clk_voltage OD_SCLK: 0: 1800Mhz * OD_VDDC: 0: 862mV * OD_RANGE: SCLK: 1000Mhz 2000Mhz VDDC: 700mV 1129mV 2) Set sclk to 1500MHz and vddc to 700mV $ echo vc 0 1500 700 > pp_od_clk_voltage $ echo c > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 1500Mhz * OD_VDDC: 0: 693mV * OD_RANGE: SCLK: 1000Mhz 2000Mhz VDDC: 700mV 1129mV 3) Reset sclk and vddc to default $ echo r > pp_od_clk_voltage $ echo c > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 1800Mhz * OD_VDDC: 0: 874mV * OD_RANGE: SCLK: 1000Mhz 2000Mhz VDDC: 700mV 1129mV NOTE: We don't specify an explicit safe range, you can set any values between min and max at your own risk. Enjoy! Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
-
Lang Yu authored
Add print_clk_levels and read_sensor pptable funcs for cyan skilfish. v2: keep consitency and add get_gpu_metrics callback. v3: use sysfs_emit_at() in sysfs show function. Signed-off-by:
-
Lang Yu authored
Add SmuMetrics_t definition for cyan skilfish. v2: update SmuMetrics_t definition. v3: cleanup and rearrange the order of fields. Signed-off-by:
-
Lang Yu authored
Add some PPSMC MSGs for cyan skilfish. Signed-off-by:
-
Lang Yu authored
sysfs_emit and sysfs_emit_at requrie a page boundary aligned buf address. Make them happy! v2: use an inline function. Warning Log: [ 492.545174] invalid sysfs_emit_at: buf:00000000f19bdfde at:0 [ 492.546416] WARNING: CPU: 7 PID: 1304 at fs/sysfs/file.c:765 sysfs_emit_at+0x4a/0xa0 [ 492.654805] Call Trace: [ 492.655353] ? smu_cmn_get_metrics_table+0x40/0x50 [amdgpu] [ 492.656780] vangogh_print_clk_levels+0x369/0x410 [amdgpu] [ 492.658245] vangogh_common_print_clk_levels+0x77/0x80 [amdgpu] [ 492.659733] ? preempt_schedule_common+0x18/0x30 [ 492.660713] smu_print_ppclk_levels+0x65/0x90 [amdgpu] [ 492.662107] amdgpu_get_pp_od_clk_voltage+0x13d/0x190 [amdgpu] [ 492.663620] dev_attr_show+0x1d/0x40 Signed-off-by:
-
Anson Jacob authored
Assert only when FPU is not enabled. Fixes: 0ea7ee82 ("drm/amd/display: Add DC_FP helper to check FPU state") Signed-off-by:
Anson Jacob <Anson.Jacob@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
-
John Clements authored
Added trigger error support for MP0/MP1/MPIO blocks Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
-
John Clements authored
Remove uncessary RAS status prints Reviewed-by:
-
Likun Gao authored
Refactor the code of amdgpu_ucode_init_single_fw to make it more readable as too many ucode need to handle on this function currently. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
-
Nicholas Kazlauskas authored
[Why] If we're running a headless config with 0 links then the vblank workqueue will be NULL - causing a NULL pointer exception during any commit. [How] Guard access to the workqueue if it's NULL and don't queue or flush work if it is. Reported-by:
Mike Lothian <mike@fireburn.co.uk> BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1700 Fixes: 58aa1c50 ("drm/amd/display: Use vblank control events for PSR enable/disable") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
-
Roy Sun authored
Enable sysnode vclk and dclk on Navi21 asic for guest smi Signed-off-by:
Roy Sun <Roy.Sun@amd.com> Reviewed-by:
Emily.Deng <Emily.Deng@amd.com> Signed-off-by:
-
Nirmoy Das authored
Use debugfs_create_file_size API for creating ring debugfs, and as its a NULL returning API, change the return type for amdgpu_debugfs_ring_init API as well. Also cleanup surrounding code. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Shashank Sharma <shashank.sharma@amd.com> Signed-off-by:
-
Nirmoy Das authored
debugfs APIs returns encoded error so use IS_ERR for checking return value. v2: return PTR_ERR(ent) References: https://gitlab.freedesktop.org/drm/amd/-/issues/1686Signed-off-by:
-
- 07 Sep, 2021 11 commits
-
-
chongjiapeng authored
drm/amd/display: make configure_lttpr_mode_transparent and configure_lttpr_mode_non_transparent static This symbols is not used outside of dc_link_dp.c, so marks it static. Fix the following sparse warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1766:16: warning: symbol 'configure_lttpr_mode_non_transparent' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:1755:16: warning: symbol 'configure_lttpr_mode_transparent' was not declared. Should it be static? Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
chongjiapeng <jiapeng.chong@linux.alibaba.com> Signed-off-by:
-
chongjiapeng authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c:643:35-36: WARNING comparing pointer to 0. Reported-by:
-
Colin Ian King authored
The variables hi_sidd and lo_sidd are being initialized with a values that are never read, they are being updated later on. The assignments are redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
-
Simon Ser authored
In amdgpu_dm_atomic_check, dc_validate_global_state is called. On failure this logs a warning to the kernel journal. However warnings shouldn't be used for atomic test-only commit failures: user-space might be perfoming a lot of atomic test-only commits to find the best hardware configuration. Downgrade the log to a regular DRM atomic message. While at it, use the new device-aware logging infrastructure. This fixes error messages in the kernel when running gamescope [1]. [1]: https://github.com/Plagman/gamescope/issues/245Reviewed-by:
Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <hwentlan@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
-
Len Baker authored
As noted in the "Deprecated Interfaces, Language Features, Attributes, and Conventions" documentation [1], size calculations (especially multiplication) should not be performed in memory allocator (or similar) function arguments due to the risk of them overflowing. This could lead to values wrapping around and a smaller allocation being made than the caller was expecting. Using those allocations could lead to linear overflows of heap memory and other misbehaviors. So, refactor the code a bit to use the purpose specific kcalloc() function instead of the calculated size argument in the kzalloc() function. [1] https://www.kernel.org/doc/html/v5.14/process/deprecated.html#open-coded-arithmetic-in-allocator-argumentsSigned-off-by:
Len Baker <len.baker@gmx.com> Signed-off-by:
-
Colin Ian King authored
There is a statement that is indented incorrectly. Clean it up. Reviewed-by:
-
Colin Ian King authored
There are a couple of statements that are indented one character too deeply, clean these up. Reviewed-by:
-
Christian König authored
Just drop some dead code. Signed-off-by:
-
Christian König authored
The memory backing old_mem is already freed at that point, move the check a bit more up. Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
-
Candice Li authored
Creat common PSP TA load function and update PSP ta_mem_context with size information. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
-
Kenneth Feng authored
fix the issue of uploading powerplay table due to the dependancy of rlc. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Jack Gui <Jack.Gui@amd.com> Signed-off-by:
-
- 02 Sep, 2021 1 commit
-
-
Ernst Sjöstrand authored
Seems like newer cards can have even more instances now. Found by UBSAN: array-index-out-of-bounds in drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:318:29 index 8 is out of range for type 'uint32_t *[8]' Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1697 Cc: stable@vger.kernel.org Signed-off-by:
Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by:
-
- 01 Sep, 2021 14 commits
-
-
Colin Ian King authored
Pointer sink is being inintialized with a value that is never read, it is later being re-assigned a new value. Remove the redundant initialization. Addresses-Coverity: ("Unused value") Signed-off-by: -
Yifan Zha authored
[Why] Sending invalid SMU message in sriov cause set dpm level fail. [How] Update message table based on SMU firmware. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Review-by:
Horace Chen <Horace.Chen@amd.com> Signed-off-by:
-
Satyajit Sahu authored
Schedule the encode job in VCE/VCN encode ring based on the priority set by UMD. Signed-off-by:
Satyajit Sahu <satyajit.sahu@amd.com> Reviewed-by:
-
Satyajit Sahu authored
VCN has multiple rings. Set the proper priority level for each encode ring while initializing. Signed-off-by:
-
Satyajit Sahu authored
VCE has multiple rings. Set the proper priority level for each ring while initializing. Signed-off-by:
-
Candice Li authored
Add MPIO to RAS block Signed-off-by:
-
Candice Li authored
Create common PSP TA unload function and replace all common TA unloading sequences. Signed-off-by:
-
Tom St Denis authored
This new debugfs interface uses an IOCTL interface in order to pass along state information like SRBM and GRBM bank switching. This new interface also allows a full 32-bit MMIO address range which the previous didn't. With this new design we have room to grow the flexibility of the file as need be. (v2): Move read/write to .read/.write, fix style, add comment for IOCTL data structure (v3): C style comments (v4): use u32 in struct and remove offset variable (v5): Drop flag clearing in op function, use 0xFFFFFFFF for broadcast instead of 0x3FF, use mutex for op/ioctl. Signed-off-by:Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
-
Colin Ian King authored
There is a spelling mistake in a DC_LOG_WARNING message. Fix it. Reviewed-by:
-
Nirmoy Das authored
Currently AMDGPU_RING_PRIO_MAX is redefinition of a max gfx hwip priority, this won't work well when we will have a hwip with different set of priorities than gfx. Also, HW ring priorities are different from ring priorities. Create a global enum for ring priority levels which each HWIP can use to define its own priority levels. Signed-off-by:
-
Nirmoy Das authored
To get a hardware queue priority for a context, we are currently mapping AMDGPU_CTX_PRIORITY_* to DRM_SCHED_PRIORITY_* and then to hardware queue priority, which is not the right way to do that as DRM_SCHED_PRIORITY_* is software scheduler's priority and it is independent from a hardware queue priority. Use userspace provided context priority, AMDGPU_CTX_PRIORITY_* to map a context to proper hardware queue priority. Signed-off-by:
-
Aric Cyr authored
This version brings along following fixes: - FW promotion 0.0.80 - Add missing ABM register offsets - Fix in swizzle mode mapping - Emulated sink support for freesync - Improvoments in max target bpp Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by:
-
Anthony Koo authored
- Add volatile to avoid incomplete flushing of data in rb Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Tested-by:
-
Alvin Lee authored
[Why] Swizzle mode enum for DC_SW_VAR_R_X was existing, but not mapped correctly. [How] Update mapping and conversion for DC_SW_VAR_R_X. Reviewed-by:
XiangBing Foo <XiangBing.Foo@amd.com> Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Alvin Lee <Alvin.Lee2@amd.com> Cc: stable@vger.kernel.org Tested-by:
-
