- 21 Dec, 2020 5 commits
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Stephen Boyd authored
Merge branches 'clk-ingenic', 'clk-vc5', 'clk-cleanup', 'clk-canaan' and 'clk-marvell' into clk-next - Bindings for Canaan K210 SoC clks * clk-ingenic: clk: ingenic: Fix divider calculation with div tables * clk-vc5: clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" * clk-cleanup: clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: bcm: dvp: Add MODULE_DEVICE_TABLE() clk: bcm: dvp: drop a variable that is assigned to only * clk-canaan: dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix * clk-marvell: clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
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Stephen Boyd authored
- Add some trace points for clk_set_rate() "range" functions - DVFS support for AT91 clk driver * clk-ti: clk: ti: omap5: Fix reboot DPLL lock failure when using ABE TIMERs clk: ti: Fix memleak in ti_fapll_synth_setup * clk-analog: clk: axi-clkgen: move the OF table at the bottom of the file clk: axi-clkgen: wrap limits in a struct and keep copy on the state object dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format * clk-trace: clk: Trace clk_set_rate() "range" functions * clk-at91: clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error * clk-silabs: clk: si5351: Wait for bit clear after PLL reset
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Stephen Boyd authored
- Support for SiFive FU740 PRCI - Add hardware enable information to clk_summary debugfs * clk-tegra: clk: tegra: Fix duplicated SE clock entry clk: tegra: bpmp: Clamp clock rates on requests clk: tegra: Do not return 0 on failure * clk-imx: (24 commits) clk: imx: scu: remove the calling of device_is_bound clk: imx: scu: Make pd_np with static keyword clk: imx8mq: drop of_match_ptr from of_device_id table clk: imx8mp: drop of_match_ptr from of_device_id table clk: imx8mn: drop of_match_ptr from of_device_id table clk: imx8mm: drop of_match_ptr from of_device_id table clk: imx: gate2: Remove unused variable ret clk: imx: gate2: Add locking in is_enabled op clk: imx: gate2: Add cgr_mask for more flexible number of control bits clk: imx: gate2: Check if clock is enabled against cgr_val clk: imx: gate2: Keep the register writing in on place clk: imx: gate2: Remove the IMX_CLK_GATE2_SINGLE_BIT special case clk: imx: scu: fix build break when compiled as modules clk: imx: remove redundant assignment to pointer np clk: imx: remove unneeded semicolon clk: imx: lpcg: add suspend/resume support clk: imx: clk-imx8qxp-lpcg: add runtime pm support clk: imx: lpcg: allow lpcg clk to take device pointer clk: imx: imx8qxp-lpcg: add parsing clocks from device tree clk: imx: scu: add suspend/resume support ... * clk-sifive: clk: sifive: Add clock enable and disable ops clk: sifive: Fix the wrong bit field shift clk: sifive: Add a driver for the SiFive FU740 PRCI IP block clk: sifive: Use common name for prci configuration clk: sifive: Extract prci core to common base dt-bindings: fu740: prci: add YAML documentation for the FU740 PRCI * clk-mediatek: clk: mediatek: Make mtk_clk_register_mux() a static function * clk-summary: clk: Add hardware-enable column to clk summary
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Stephen Boyd authored
Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and 'clk-unused' into clk-next - Replace clk-provider.h with of_clk.h when possible * clk-amlogic: clk: meson: g12a: add MIPI DSI Host Pixel Clock dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings clk: meson: enable building as modules clk: meson: Kconfig: fix dependency for G12A clk: meson: axg: add MIPI DSI Host clock clk: meson: axg: add Video Clocks dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding dt-bindings: clk: axg-clkc: add Video Clocks * clk-rockchip: clk: rockchip: fix i2s gate bits on rk3066 and rk3188 clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks clk: rockchip: Remove redundant null check before clk_prepare_enable clk: rockchip: Add appropriate arch dependencies * clk-of: xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h> sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h> * clk-freescale: clk: fsl-flexspi: new driver dt-bindings: clock: document the fsl-flexspi-clk device clk: divider: add devm_clk_hw_register_divider_table() clk: qoriq: provide constants for the type clk: fsl-sai: use devm_clk_hw_register_composite_pdata() clk: composite: add devm_clk_hw_register_composite_pdata() clk: fsl-sai: fix memory leak clk: qoriq: Add platform dependencies * clk-unused: clk: scpi: mark scpi_clk_match as maybe unused clk: pwm: drop of_match_ptr from of_device_id table
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Stephen Boyd authored
Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', 'clk-renesas' and 'clk-samsung' into clk-next - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw * clk-doc: clk: fix a kernel-doc markup * clk-qcom: (27 commits) clk: qcom: rpmh: add support for SM8350 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8350 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180 clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks clk: qcom: Add GDSC support for SDX55 GCC dt-bindings: clock: Add GDSC in SDX55 GCC clk: qcom: Add support for SDX55 RPMh clocks dt-bindings: clock: Introduce RPMHCC bindings for SDX55 clk: qcom: Add SDX55 GCC support dt-bindings: clock: Add SDX55 GCC clock bindings clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic" clk: qcom: rpmh: Add CE clock on sdm845. dt-bindings: clock: Add entry for crypto engine RPMH clock resource clk: qcom: dispcc-sm8250: handle MMCX power domain clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init() clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks dt-bindings: clock: Add support for LPASS Always ON Controller ... * clk-simplify: clk: remove unneeded dead-store initialization * clk-hw: clk: meson: g12: use devm variant to register notifiers clk: add devm variant of clk_notifier_register clk: meson: g12: drop use of __clk_lookup() clk: add api to get clk consumer from clk_hw clk: avoid devm_clk_release name clash * clk-renesas: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI * clk-samsung: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
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- 20 Dec, 2020 4 commits
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Damien Le Moal authored
Document the device tree bindings of the Canaan Kendryte K210 SoC clock driver in Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml. The header file include/dt-bindings/clock/k210-clk.h is modified to include the complete list of IDs for all clocks of the SoC. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201220085725.19545-3-damien.lemoal@wdc.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Damien Le Moal authored
Update Documentation/devicetree/bindings/vendor-prefixes.yaml to include "canaan" as a vendor prefix for "Canaan Inc.". Canaan is the vendor of the Kendryte K210 RISC-V SoC. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201220085725.19545-2-damien.lemoal@wdc.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Geert Uytterhoeven authored
Commit 45c94018 ("dt-bindings: clk: versaclock5: convert to yaml") accidentally changed "idt,voltage-microvolts" to "idt,voltage-microvolt" in the DT bindings, while the driver still used the former. Update the driver to match the bindings, as Documentation/devicetree/bindings/property-units.txt actually recommends using "microvolt". Fixes: 260249f9 ("clk: vc5: Enable addition output configurations of the Versaclock") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201218125253.3815567-1-geert+renesas@glider.beReviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Paul Cercueil authored
The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock. Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise. Fixes: a9fa2893 ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.netSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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- 19 Dec, 2020 18 commits
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Jernej Skrabec authored
Two clock divider tables are missing sentinel at the end. Effect of that is that clock framework reads past the last entry. Fix that with adding sentinel at the end. Issue was discovered with KASan. Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks") Fixes: c6a06374 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Link: https://lore.kernel.org/r/20201202203817.438713-1-jernej.skrabec@siol.netAcked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Christophe JAILLET authored
Some resource should be released in the error handling path of the probe function, as already done in the remove function. The remove function was fixed in commit bf416bd4 ("clk: s2mps11: Add missing of_node_put and of_clk_del_provider") Fixes: 7cc560de ("clk: s2mps11: Add support for s2mps11") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20201212122818.86195-1-christophe.jaillet@wanadoo.frReviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Terry Zhou authored
There is an error in the current code that the XTAL MODE pin was set to NB MPP1_31 which should be NB MPP1_9. The latch register of NB MPP1_9 has different offset of 0x8. Signed-off-by: Terry Zhou <bjzhou@marvell.com> [pali: Fix pin name in commit message] Signed-off-by: Pali Rohár <pali@kernel.org> Fixes: 7ea82504 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.orgReviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Sascha Hauer authored
Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits are self clearing bits, so wait until they are cleared before continuing. This fixes a case when the clock doesn't come up properly after a PLL reset. It worked properly when the frequency was below 900MHz, but with 900MHz it only works when we are waiting for the bit to clear. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20201130091033.1687-1-s.hauer@pengutronix.deSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Alexandre Belloni authored
The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator bypass. Fixes: 01e2113d ("clk: at91: add sam9x60 pmc driver") Reported-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.comReviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
Register CPU clock as being the master clock prescaler. This would be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the frequencies supported by SAMA7G5 could be directly received from CPUPLL + master clock prescaler and the extra divider would do no work in case it would be enabled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
Re-factor master clock driver by splitting it into 2 clocks: prescaller and divider clocks. Based on registered clock flags the prescaler's rate could be changed at runtime. This is necessary for platforms supporting DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is also changed by DVFS to avoid over/under clocking of MCK0 consumers. The lower limit is changed to be able to set MCK0 accordingly by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
MCK0 is changed at runtime by DVFS. Due to this, since not all IPs are glitch free aware at MCK0 changes, remove MCK0 from parent list of other clocks (e.g. generic clock, programmable/system clock, MCKX). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
Allow runtime frequency changes for PLLs registered with proper flags. This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Eugen Hristev authored
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Eugen Hristev authored
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Eugen Hristev authored
Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock from phandle in DT. Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Eugen Hristev authored
Add SAMA7G5 specific PLL defines to be referenced in a phandle as a PMC_TYPE_CORE clock. Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Claudiu Beznea authored
pmc_data_allocate() has been changed. pmc_data_free() was removed. Adapt the code taking this into consideration. With this the programmable clocks were also saved in sama7g5_pmc so that they could be later referenced. Fixes: cb783bbb ("clk: at91: sama7g5: add clock support for sama7g5") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-2-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Nicolas Saenz Julienne authored
Add MODULE_DEVICE_TABLE() so as to be able to use the driver as a module. More precisely, for the driver to be loaded automatically at boot. Fixes: 1bc95972 ("clk: bcm: Add BCM2711 DVP driver") Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Link: https://lore.kernel.org/r/20201202103518.21889-1-nsaenzjulienne@suse.deReviewed-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Uwe Kleine-König authored
The third parameter to devm_platform_get_and_ioremap_resource() is used only to provide the used resource. As this variable isn't used afterwards, switch to the function devm_platform_ioremap_resource() which doesn't provide this output parameter. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20201120132121.2678997-1-u.kleine-koenig@pengutronix.deReviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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- 17 Dec, 2020 8 commits
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Maxime Ripard authored
The clk_set_rate "range" functions don't have any tracepoints even though it might be useful. Add some. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201207105050.2096917-1-maxime@cerno.tech [sboyd@kernel.org: Reword commit text] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Alexandru Ardelean authored
The change is mostly cosmetic. No functional changes. Since the driver now uses of_device_get_match_data() to obtain some driver specific info, there is no need to define the OF table before the probe function. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-2-alexandru.ardelean@analog.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Alexandru Ardelean authored
Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Alexandru Ardelean authored
This change converts the old binding for the AXI clkgen driver to a yaml format. As maintainers, added: - Lars-Peter Clausen <lars@metafoo.de> - as original author of driver & binding - Michael Hennerich <michael.hennerich@analog.com> - as supporter of Analog Devices drivers Acked-by: Michael Hennerich <michael.hennerich@analog.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201013143421.84188-1-alexandru.ardelean@analog.comReviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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David Shah authored
Having the ABE DPLL ref and bypass muxes set to different inputs was causing the DPLL not to lock when TIMER8 was used, as it is in the Pyra for the backlight. This patch fixes this by setting abe_dpll_bypass_clk_mux to sys_32k_ck in omap5xxx_dt_clk_init. A similar patch may also be needed for OMAP44xx which has similar code in omap4xxx_dt_clk_init, but I have not added this as I have no hardware to test on. Signed-off-by: David Shah <dave@ds0.me> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/r/1d3abe2512054866cc2ea7b2592238f4fa06502a.1607253531.git.hns@goldelico.comAcked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Zhang Qilong authored
If clk_register fails, we should goto free branch before function returns to prevent memleak. Fixes: 163152cb ("clk: ti: Add support for FAPLL on dm816x") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20201113131623.2098222-1-zhangqilong3@huawei.comAcked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Dmitry Osipenko authored
Add "hardware enable" column to the clk summary in order to show actual hardware enable-state of all clocks. The possible states are "Y/N/?", where question mark means that state is unknown, i.e. clock isn't a mux and clk-driver doesn't support is_enabled() callback for this clock. In conjunction with clk_ignore_unused, this tells us what unused clocks are left enabled after bootloader. This is also a useful aid for debugging interactions with firmware which changes clock states without notifying kernel. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Link: https://lore.kernel.org/r/20201115203432.13934-1-digetx@gmail.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Weiyi Lu authored
mtk_clk_register_mux() should be a static function Fixes: a3ae5499 ("clk: mediatek: Add new clkmux register API") Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Link: https://lore.kernel.org/r/1605256192-31307-1-git-send-email-weiyi.lu@mediatek.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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- 16 Dec, 2020 5 commits
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Pragnesh Patel authored
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable() and sifive_clk_is_enabled()" to enable or disable the PRCI clock Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Zong Li <zong.li@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-6-zong.li@sifive.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Zong Li authored
The clk enable bit should be 31 instead of 24. Signed-off-by: Zong Li <zong.li@sifive.com> Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Zong Li authored
Add driver code for the SiFive FU740 PRCI IP block. This IP block handles reset and clock control for the SiFive FU740 device and implements SoC-level clock tree controls and dividers. The link of unmatched as follow, and the U740-C000 manual would be present in the same page as soon. https://www.sifive.com/boards/hifive-unmatched This driver contains bug fixes and contributions from Henry Styles <hes@sifive.com> Erik Danie <erik.danie@sifive.com> Pragnesh Patel <pragnesh.patel@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Henry Styles <hes@sifive.com> Cc: Erik Danie <erik.danie@sifive.com> Cc: Pragnesh Patel <pragnesh.patel@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-4-zong.li@sifive.com [sboyd@kernel.org: Include header to silence sparse] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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Zong Li authored
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This patch is prepared for fu740 support. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Link: https://lore.kernel.org/r/20201209094916.17383-3-zong.li@sifive.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
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Zong Li authored
Extract common core of prci driver to an independent file, it could allow other chips to reuse it. Separate SoCs-dependent code 'fu540' from prci core, then we can easily add 'fu740' later. Almost these changes are code movement. The different is adding the private data for each SoC use, so it needs to get match data in probe callback function, then use the data for initialization. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Link: https://lore.kernel.org/r/20201209094916.17383-2-zong.li@sifive.com [sboyd@kernel.org: Include header to silence sparse] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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