- 11 Sep, 2012 1 commit
-
-
Gavin Shan authored
This patch implements a weak function to return the default I/O or memory window alignment for a P2P bridge. By default, I/O windows are aligned to 4KiB or 1KiB and memory windows are aligned to 4MiB. Some platforms, e.g., powernv, have special alignment requirements and can override pcibios_window_alignment(). [bhelgaas: changelog] Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
- 23 Aug, 2012 39 commits
-
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify rtl8192e driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify et131x driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify tsi721 driver. [bhelgaas: use word (16-bit) accesses for PCI_EXP_DEVCTL, PCI_EXP_DEVCTL2] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alexandre Bounine <alexandre.bounine@idt.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify radeon driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify qla4xxx driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify qla2xxx driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify qib driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify mthca driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roland Dreier <roland@purestorage.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify rtlwifi driver. [bhelgaas: split iwlegacy, iwlwifi, rtlwifi into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify iwlwifi driver. [bhelgaas: split iwlegacy, iwlwifi, rtlwifi into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify iwlegacy driver. [bhelgaas: split iwlegacy, iwlwifi, rtlwifi into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify ath9k driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify atl1c driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify cxgb4 driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify cxgb3 driver. [bhelgaas: split cxgb3 and cxgb4 into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify myri10ge driver. [bhelgaas: fix myri10ge_toggle_relaxed() return value] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify niu driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify mlx4 driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify vxge driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify igb driver. [bhelgaas: split e1000e and igb into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify e1000e driver. [bhelgaas: split e1000e and igb into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify tg3 driver. [bhelgaas: split bnx2x and tg3 into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify bnx2x driver. [bhelgaas: split bnx2x and tg3 into separate patches] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Bjorn Helgaas authored
Previously, when we turned on the "Enable No Snoop Bit," we cleared all the other Device Control bits, including error reporting enables, Max_Payload_Size, Max_Read_Request_Size, etc. This patch preserves all the other bits. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify r8169 driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify Tile PCIe code. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify MIPS PCIe code. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: David Daney <david.daney@cavium.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify ARM PCIe code. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify PCIe ASPM. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify PCIe AER. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify PCIe PME. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify pciehp. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify portdrv. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify pcihp_slot.c. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
-
Bjorn Helgaas authored
Before initiating an FLR, we should wait for completion of any outstanding non-posted requests. See PCIe spec r3.0, sec 6.6.2. This makes reset_intel_82599_sfp_virtfn() very similar to the generic pcie_flr(). The only difference is that the 82599 doesn't report FLR support in the VF Device Capability register. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
Use PCI Express Capability access functions to simplify core. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Jiang Liu authored
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and r1.1), some fields are optional, so the structure size depends on the device type. This patch adds functions to access this capability so drivers don't have to be aware of the differences between v1 and v2. Note that these new functions apply only to the "PCI Express Capability," not to any of the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) Function pcie_capability_read_word/dword() reads the PCIe Capabilities register and returns the value in the reference parameter "val". If the PCIe Capabilities register is not implemented on the PCIe device, "val" is set to 0. Function pcie_capability_write_word/dword() writes the value to the specified PCIe Capability register. Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits of a PCIe Capability register. [bhelgaas: changelog, drop "pci_" prefixes, don't export pcie_capability_reg_implemented()] Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Yijing Wang authored
With introduction of pci_pcie_type(), pci_dev->pcie_type field becomes redundant, so remove it. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-
Yijing Wang authored
Introduce an inline function pci_pcie_type(dev) to extract PCIe device type from pci_dev->pcie_flags_reg field, and prepare for removing pci_dev->pcie_type. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-