- 30 Jul, 2014 40 commits
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Atsushi Nemoto authored
Fix wrong code spotted by -Werror=array-bounds: arch/mips/txx9/generic/pci.c:334:23: error: array subscript is above array bounds [-Werror=array-bounds] pci_write_config_byte(dev, regs[i], dat); Signed-off-by:
Atsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7214/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Maciej W. Rozycki authored
This fixes a regression caused by commit bb6c0bd3 [MIPS: SB1: Fix excessive kernel warnings.], that makes `-march=r5000' selected for compilation flags rather than supposed `-march=sb1' with compilers that do not support the ASE selection flags introduced with that change. For example GCC 4.1.2 supports `-mips3d'/`-mno-mips3d' (and obviously `-march=sb1'), however it does not support `-mdmx'/`-mno-mdmx'. As a result the whole selection of flags fails and compilation resorts to using `-march=r5000', meant for really old compilers indeed only. It is always best to pick the flags individually unless we are absolutely sure a set of flags was introduced to the toolchain together (`-march=sb1' and `-mtune=sb1' would be a good example), and this change makes it happen for CONFIG_CPU_SB1. Consequently the flags ultimately selected with GCC 4.1.2 are `-march=sb1 -Wa,--trap -mno-mips3d' Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: Richard Sandiford <rdsandiford@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7223/Signed-off-by:
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Maciej W. Rozycki authored
This fixes: {standard input}: Assembler messages: {standard input}:145: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2' {standard input}:920: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$9' {standard input}:1797: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:1851: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:2831: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:4209: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:4329: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2' make[2]: *** [arch/mips/mm/tlbex.o] Error 1 which triggered due to a regression causing the file to be built with `-march=r5000' rather than `-march=sb1', fixed separately. Nevertheless the error should not happen, the other uses of CLZ are appropriately guarded. This change copies the arrangement from one of those other places. Signed-off-by: -
Maciej W. Rozycki authored
Code in a switch statement in probe_pcache checks the CPU type twice unnecessarily for processor implementations that have the alias removal feature reported by the CP0 Config7.AR and Config7.IAR bits. This change rewrites the affected fragment avoiding the extraneous check and improving readability. Signed-off-by:
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Jonas Gorski authored
Wire up the set_affinity call for the internal PIC if booting on a cpu supporting it. Affinity is kept to boot cpu as default. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7323/Signed-off-by:
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Jonas Gorski authored
In preparation for applying affinity, use the irq descriptor as the argument for (un)mask. Signed-off-by:
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Jonas Gorski authored
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Jonas Gorski authored
Since we will have the chance of accessing the registers concurrently, protect any accesses through a spinlock. Signed-off-by:
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Jonas Gorski authored
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Jonas Gorski authored
Set it to zero if there is no second set. Signed-off-by:
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Jonas Gorski authored
The SMP capable irq controllers have two interrupt output pins which are controlled through separate registers, so make the variables arrays. Signed-off-by:
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Jonas Gorski authored
The generic version uses a variable length of u32 registers instead of u32/u64. This allows easier support for "wider" registers without having to rewrite everything. This "generic" version is as fast as the old version in the best case (i == next set bit), and twice as fast in the worst case in 64 bits. Using a macro was chosen over a (forced) inline version because gcc generated more compact code with the macro. The change from (signed) int to unsigned int for i and to_call was intentional as the value can be only between 0 and (width - 1) anyway, and allowed gcc to optimise the code a bit further. Signed-off-by:
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Jonas Gorski authored
Allows up to drop the prototypes from the top. Signed-off-by:
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Jonas Gorski authored
Make it follow the same naming convention as the other functions. Signed-off-by:
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Jonas Gorski authored
Use the same pattern as with get_*_cpu_type() to allow the compiler to remove code for non enabled SoC types. Signed-off-by:
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Jonas Gorski authored
All three SoCs have in common they have a BMIPS32/BMIPS3300 CPU, so we can replace this as no SoC with BMIPS4350 support enabled. Signed-off-by:
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Jonas Gorski authored
Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7270/Signed-off-by:
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Jonas Gorski authored
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Jonas Gorski authored
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Jonas Gorski authored
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Jonas Gorski authored
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Jonas Gorski authored
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Jonas Gorski authored
We are using the mips counters as the clock source, so we need to ensure they are synced, else e.g. gettimeofday will return different values depending on which core it was run. Observed difference was about 8 seconds, causing ~8 seconds ping or time running backwards for some programs. Signed-off-by:
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Rickard Strandqvist authored
Replacing strncpy with strlcpy to avoid strings that lacks null terminate. Signed-off-by:
Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Cc: Rob Herring <robh@kernel.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7485/Signed-off-by:
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Manuel Lauss authored
With the clock framework in place, remove unused functions and bits, and drop the CLK_IGNORE_UNUSED flag, which is now unneeded. Signed-off-by:
Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7473/Signed-off-by:
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Manuel Lauss authored
Use the clock framework to get the peripheral clock rate to correctly set the MMC/SD bus clock divider. Signed-off-by:
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Manuel Lauss authored
minimal patch to replace direct clock register hackery with clock framework calls. Signed-off-by:
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Manuel Lauss authored
Use the clock framework to en/disable the clock to the au1100 framebuffer device. Signed-off-by:
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Manuel Lauss authored
Test the existence of the irda_clk clock object, use it to en/dis- able it when date is being transferred. Signed-off-by:
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Manuel Lauss authored
Make use of the clk framework to set up and enable all PSC clocks. Signed-off-by:
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Manuel Lauss authored
Use the clock framework to get at the PCI clock source and enable it on driver initialization. Signed-off-by:
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Manuel Lauss authored
Add use of the common clock framework to set and enable the 48MHz clock source for the onchip OHCI and UDC blocks. Tested on a DB1500. (Au1200 and Au1300 use an external 48MHz crystal). Signed-off-by:
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Manuel Lauss authored
Use the clock framework to get the rate of the peripheral clock. Remove the now obsolete get_uart_baud_base function. Signed-off-by:
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Manuel Lauss authored
This patch introduces common clock framework integration for all configurable on-chip clocks on Alchemy chips: - 2 or 3 PLLs which generate integer multiples of the root rate 12MHz, - 6 dividers which take one of the 3 PLLs as input and divide their rate by either multiples of 2 or 1 (Au1300). - another bank of up to 6 muxes which take either one of the 6 above dividers or one of the PLLs directly and divide their rate further by 1, 2, 3 or 4. - a few other sources which are used by onchip peripherals and are informational. This implementation will take the clock tree as it was set up by boot firmware: all in-kernel boards should continue to work without having to set up the clock tree in board code. CLK_IGNORE_DISABLED will be removed once all drivers have been converted. Signed-off-by:
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Manuel Lauss authored
replace au_read/write/sync with __raw_read/write and wmb. Signed-off-by:
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Manuel Lauss authored
This patch changes the static memory controller registers to offsets from base, prefixes them with AU1000_ to avoid silent failures due to changed addresses and introduces helpers to access them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by:
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Manuel Lauss authored
This patch changes all absolute SYS_XY registers to offsets from the SYS block base, prefixes them with AU1000 to avoid silent failures due to changed addresses, and introduces helper functions to read/write them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by:
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Manuel Lauss authored
Move the C-code after all macros: A follow-on patch which introduces helpers to access the SYS_* registers needs this to build. Just code shuffling, no functional changes. Signed-off-by:
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Manuel Lauss authored
Move the register offsets and bit descriptions from the au1000.h header to their only user, the au1000_eth.c driver. Signed-off-by:
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Manuel Lauss authored
Remove the unused SSI I2S and AC97C register definitions. Signed-off-by:
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