- 08 Oct, 2018 40 commits
-
-
Linus Walleij authored
This driver is complicating things for no reason: the "cd" GPIO can easily be retrieved from the device tree if present using just mmc_gpiod_request_cd(), which will fetch the descriptor from the device tree using the standard binding just fine. Cc: Viresh Kumar <vireshk@kernel.org> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
-
Linus Walleij authored
All the machines using the MMCI are passing GPIOs for the card detect and write protect using the device tree or descriptor table (one single case, Integrator/AP IM-PD1). Drop support for passing global GPIO numbers through platform data, noone is using it. Signed-off-by:
-
Jisheng Zhang authored
If hosts provides ops->adma_write_desc, we should not fall back to the general sdhci_adma_write_desc(). Signed-off-by:
Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
-
jun qian authored
As you are already in ISR, it is unnecessary to call spin_lock_irqsave. Signed-off-by:
jun qian <hangdianqj@163.com> Reviewed-by:
Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
-
Niklas Söderlund authored
Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a device_dma_parameters structure and filling in the max segment size. The size used is the result of a discussion with Renesas hardware engineers and unfortunately not found in the datasheet. renesas_sdhi_internal_dmac ee140000.sd: DMA-API: mapping sg segment longer than device claims to support [len=126976] [max=65536] Reported-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [wsa: simplified some logic after validating intended dma_parms life cycle and added comment] Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
-
Chen-Yu Tsai authored
The eMMC controller is also a new timing mode controller, but it doesn't have the timing mode switch. It does however have signal delay and calibration controls, typical of Allwinner MMC controllers that support the new timing mode. Enable the new timing mode setting for the A64 eMMC controller. This also enables MMC HS-DDR modes, which gives higher throughput for eMMC chips that support it, and can deliver such throughput. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
-
Chen-Yu Tsai authored
Newer sunxi mmc controller variants support what they call the "new timing mode". Support for this was implemented in two ways, according to the hardware that was seen at the time. The first type retained the old timing mode, and both the clock and mmc controllers had switches to select which mode was used. Both switches had to be set to the same setting. This variant was denoted with the .has_timings_switch field in the sunxi_mmc_cfg structure. This hardware is only seen on the A83T. The second type did away with the old timing mode. The clock controller no longer had the mode selection or clock delay setting bits. In some cases the mmc controller retained its mode selection bit, but this always needed to be set to the new mode, or instabilities would occur. In a few cases, such as the A64 and H6 eMMC controller, the mode selection bit is gone, but the controller still behaves like the new timing mode, requiring the module clock to be double the card clock in DDR transfer modes. This variant is denoted with the .needs_new_timings field. This patch adds more comments explaining the two fields, as well as the possibly nonexistent mode switch in the mmc controller. The .has_timings_switch is renamed to .ccu_has_timings_switch to clarify its meaning. Signed-off-by:
-
Chunyan Zhang authored
This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by:
Billows Wu <billows.wu@unisoc.com> Signed-off-by:
Chunyan Zhang <chunyan.zhang@unisoc.com> Acked-by:
-
Chunyan Zhang authored
This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by:
-
Chunyan Zhang authored
When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by:
Chunyan Zhang <zhang.chunyan@linaro.org> Acked-by:
-
Chunyan Zhang authored
As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by:
-
Chunyan Zhang authored
Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by:
-
Chunyan Zhang authored
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by:
-
Chunyan Zhang authored
According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by:
-
Chunyan Zhang authored
For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by:
-
Chunyan Zhang authored
Added definitions for v400, v410, v420. Signed-off-by:
-
YueHaibing authored
Fix inconsistent IS_ERR and PTR_ERR in tegra_sdhci_init_pinctrl_info, the proper pointer to be passed as argument is 'pinctrl_state_1v8' Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Aapo Vienamo <aapo.vienamo@iki.fi> Signed-off-by:
-
Aapo Vienamo authored
Rerun the pad calibration procedure before sdhci_request() if the 100 ms recalibration interval has been exceeded. Signed-off-by:
Aapo Vienamo <avienamo@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
-
Aapo Vienamo authored
Implement HS400 specific delay line calibration procedure. This is a Tegra specific procedure and has to be performed regardless whether enhanced strobe or HS400 tuning is used. Signed-off-by:
-
Aapo Vienamo authored
Implement eMMC HS400 enhanced strobe. Enhanced strobe is an alternative mechanism to the HS400 tuning procedure. Signed-off-by:
-
Aapo Vienamo authored
Parse and program the HS400 DQS trim value from DT. Program a fallback value in case the property is missing. Signed-off-by:
-
Aapo Vienamo authored
Document HS400 DQS trim value device tree property. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
-
Aapo Vienamo authored
Set nvquirks to enable higher speed modes. Signed-off-by:
-
Aapo Vienamo authored
Set nvquirks to enable higher speed modes. Signed-off-by:
-
Aapo Vienamo authored
Implement tegra210_sdhci_writew() to disable card clock and issue a reset when the tuning command is sent. This is done to prevent an intermittent hang with around 10 % failure rate during tuning. Add tegra186_sdhci_ops because this workaround is specific to Tegra210. Signed-off-by:
-
Aapo Vienamo authored
tegra_sdhci_writew() defers the write to SDHCI_TRANSFER_MODE until SDHCI_COMMAND is written. This is not necessary on Tegra210 and Tegra186 and it breaks read-modify-write operations on SDHCI_TRANSFER_MODE because writes to SDHCI_TRANSFER_MODE aren't visible until SDHCI_COMMAND has been written to. This results in tuning failures on Tegra210. Signed-off-by:
-
Aapo Vienamo authored
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't set the custom tuning callback used on previous SoC generations. Signed-off-by:
-
Aapo Vienamo authored
Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike the outbound tap value this does not depend on the signaling mode and needs to be only programmed once. Signed-off-by:
-
Aapo Vienamo authored
Set the default inbound timing adjustment tap value on reset and on non-tunable modes. The default tap value is not programmed on tunable modes because the tuning sequence is used instead to determine the tap value. Signed-off-by:
-
Aapo Vienamo authored
Parse the default inbound and outbound sampling trimmer values from the device tree. Signed-off-by:
-
Aapo Vienamo authored
Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by:
-
Aapo Vienamo authored
Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic pad drive strength calibration. Signed-off-by:
-
Aapo Vienamo authored
Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by:
-
Aapo Vienamo authored
Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by:
-
Aapo Vienamo authored
Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by:
-
Aapo Vienamo authored
Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by:
Mikko Perttunen <mperttunen@nvidia.com> Acked-by:
-
Aapo Vienamo authored
Configure the voltage reference used by the automatic pad drive strength calibration procedure. The value is a magic number from the TRM. Signed-off-by:
-
Aapo Vienamo authored
Implement polling with 10 ms timeout for automatic pad drive strength calibration. Signed-off-by:
-
Aapo Vienamo authored
Parse the pinctrl state and nvidia,only-1-8-v properties from the device tree. Validate the pinctrl and regulator configuration before unmasking UHS modes. Implement pad voltage state reconfiguration in the mmc start_signal_voltage_switch() callback. Add NVQUIRK_NEEDS_PAD_CONTROL and add set it for Tegra210 and Tegra186. The pad configuration is done in the mmc callback because the order of pad reconfiguration and sdhci voltage switch depend on the voltage to which the transition occurs. Signed-off-by:
-
Aapo Vienamo authored
Document the Tegra SDHCI inbound and outbound sampling trimmer values. Signed-off-by:
-
