- 10 Jul, 2012 40 commits
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Paul Gortmaker authored
This reference board dates back to 2004, and is largely a legacy EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is a more modern, better e500v2 target for people to use as a reference board with today's kernels, should they require one. Removing support for it will also allow us to remove some sbc8560 specific quirk handling in 8250 UART code, and some MTD mapping support. Cc: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Tang Yuantian authored
Signed-off-by:
Jin Qing <b24347@freescale.com> Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by:
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Tang Yuantian authored
The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use the same platform file as the p1/p2 rdb board. Overview of P2020RDB platform - DDR3 1G - NOR flash 16M - 3 Ethernet interfaces - NAND Flash 32M - SPI EEPROM 16M - SD/MMC - 2 USB ports - 4 TDM ports Signed-off-by:
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Gustavo Zacarias authored
Add EEPROM to the P1010RDB device tree. The 24c01 acts as a memory SPD so it shouldn't be overwritten without care. The 24c256 is a general purpose memory. Signed-off-by:
Gustavo Zacarias <gustavo@zacarias.com.ar> Signed-off-by:
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Sebastian Andrzej Siewior authored
This reverts commit 0c00f656. The initial commit was my fault. There are two boards out there: P2020RDB and P2020RDB-PC. I wasn't aware of that and assumed that I have a RDB board in front of me while I the RDB-PC. This patch makes it work for the RDB-PC variant and breaks it for the RDB. Now there is a device tree file available for the RDB-PC which was not there earlier. So with this revert, everything gets back to normal :) Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
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Holger Brunck authored
Add spi support for mgcoge into the platform code and the dts file. Additionaly SPIDEV is switched on in the defconfig and the updates for the newer kernel version are committed. The SPI interface is used to drive the Maxim DS3106 clock chip. Signed-off-by:
Holger Brunck <holger.brunck@keymile.com> cc: Heiko Schocher <hs@denx.de> Signed-off-by:
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Holger Brunck authored
Switch on UBIFS, HOTPLUG and TIPC and update the config to the latest kernel version. Signed-off-by:
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Christian Herzig authored
Fix RGMII workaround code in km83xx.c for MPC8360E and MPC8358E that it correctly identifes all affected SoC chip models and applies the workarounds appropriate for 2.0 and 2.1 revisions as per Freescale MPC8360ECE Errata document Rev.5(9/2011) item QE_ENET10. Signed-off-by:
Christian Herzig <christian.herzig@keymile.com> Signed-off-by:
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Holger Brunck authored
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Jerry Huang authored
Add the RTC support into the p1022ds device tree Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Acked-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
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Shengzhou Liu authored
Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and mpc85xx_smp_defconfig to support NOR, NAND flash. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by:
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Kim Phillips authored
At least for crypto/IPSec, doing so provides users with a better performance experience out of the box. Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Matias Garcia authored
Change quirk_fsl_pcie_header from __init to __devinit to ensure if we have a runtime access (like via an FPGA being loaded after boot on the PCIe link) that we dont access randomly freed memory. Signed-off-by:
Matias Garcia <mgarcia@rossvideo.com> Signed-off-by:
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Michael Ellerman authored
Matt added BPF_JIT support in commit 0ca87f05, but currently none of our defconfigs build it. Turn that sucker on. Signed-off-by:
Michael Ellerman <michael@ellerman.id.au> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Anton Blanchard authored
Add the ability to inject IOMMU faults. We enable this per device via a fail_iommu sysfs property, similar to fault injection on other subsystems. An example: ... 0003:01:00.1 Ethernet controller: Emulex Corporation OneConnect 10Gb NIC (be3) (rev 02) To inject one error to this device: echo 1 > /sys/bus/pci/devices/0003:01:00.1/fail_iommu echo 1 > /sys/kernel/debug/fail_iommu/probability echo 1 > /sys/kernel/debug/fail_iommu/times As feared, the first failure injected on the be3 results in an unrecoverable error, taking down both functions of the card permanently: be2net 0003:01:00.1: Unrecoverable error in the card Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
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Anton Blanchard authored
The DMA API debug code has hooks to verify all DMA entries have been freed at time of hot unplug. We need to call dma_debug_add_bus for this to work. Signed-off-by:
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Anton Blanchard authored
Similar to PCI, separate the bus probe from device probe. This allows us to attach bus notifiers for DMA debug and IOMMU fault injection before devices have been probed. Signed-off-by:
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Anton Blanchard authored
During boot we see a number of these warnings: vio 30000000: Warning: IOMMU dma not supported: mask 0xffffffffffffffff, table unavailable The reason for this is that we set IOMMU properties for all VIO devices even if they are not DMA capable. Only set DMA ops, table and mask for devices with a DMA window. Signed-off-by:
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Michael Neuling authored
Signed-off-by:
Michael Neuling <mikey@neuling.org> Acked-by:
Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by:
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Anton Blanchard authored
We use SIAR or regs->nip for the instruction pointer depending on the PMU configuration, but we always use regs->nip in the callchain. Use perf_instruction_pointer so the backtrace is consistent. Signed-off-by:
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Anton Blanchard authored
At the moment we always use the SIAR if the PMU supports continuous sampling. Unfortunately the SIAR and the PMU exception are not synchronised for non marked events so we can end up with callchains that dont make sense. The following patch checks the HV and PR bits for samples coming from userspace and always uses pt_regs for them. Userspace will never have interrupts off so there is no real advantage to using the SIAR for non marked events in userspace. I had experimented with a patch that did a similar thing for kernel samples but we lost a significant amount of information. I was unable to profile any of our early exception code for example. Signed-off-by:
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Anton Blanchard authored
The logic to choose whether to use the SIAR or get the information out of pt_regs is going to get more complicated, so do it once in perf_read_regs. We overload regs->result which is gross but we are already doing it with regs->dsisr. Signed-off-by:
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Anton Blanchard authored
We want to access the MMCRA_SIHV and MMCRA_SIPR bits elsewhere so create mmcra_sihv and mmcra_sipr which hide the differences between the old and new layout of the bits. Signed-off-by:
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Michael Neuling authored
Some macros use RA where when RA=R0 the values is 0, so make this the enforced mnemonic in the macro. Idea suggested by Andreas Schwab. Signed-off-by:
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Michael Neuling authored
R0 is special since it'll be 0. Signed-off-by:
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Michael Neuling authored
Enforce the use of R0-R31 in macros where possible now we have all the fixes in. R0-R31 macros are removed here so that can't be used anymore. They should not be defined anywhere. Signed-off-by:
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Michael Neuling authored
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Michael Neuling authored
Now have ___PPC_RA/B/S/T we can use it in some places. These are places where we can't use the existing defines which will soon enforce R0-R31 usage. The macros being changed here are being used in inline asm, which can't convert to enforce the R0-R31 usage. bpf_jit uses a mix of both generated and non-generated with the same code, so just convert all these to use the ___PPC_R versions which won't enforce R usage later. Signed-off-by:
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Michael Neuling authored
These are currently the same as __PPC_RA/B/S/T but we'll wrap them soon. Signed-off-by:
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Michael Neuling authored
We need to do this so we can enforce the name of a and b in called macros PPC_RA/B later. Signed-off-by:
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Michael Neuling authored
These macros are using integers where they could be using logical names since they take registers. We are going to enforce this soon, so fix these up now. Signed-off-by:
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Michael Neuling authored
LOAD_REG_ADDR define is just a wrapper around real instructions so we can just use real register names here (ie. lower case). Signed-off-by:
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Michael Neuling authored
mtocrf define is just a wrapper around the real instructions so we can just use real register names here (ie. lower case). Also remove braces in macro so this is possible. Signed-off-by:
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Benjamin Herrenschmidt authored
Move this duplicated definition to ppc_asm.h and remove the braces which prevent the use of %rN register names Signed-off-by: -
Michael Neuling authored
Merge the defines of VCPU_GPR from different places. Signed-off-by:
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Michael Neuling authored
Merge the defines of STACKFRAMESIZE, STK_REG, STK_PARAM from different places. Signed-off-by:
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Michael Neuling authored
move lbz/stbciz to ppc-opcode.h. Signed-off-by:
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Michael Neuling authored
Now all the fixes are in place, let's rock-n-roll! Signed-off-by:
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Michael Neuling authored
Anything that uses a constructed instruction (ie. from ppc-opcode.h), need to use the new R0 macro, as %r0 is not going to work. Also convert usages of macros where we are just determining an offset (usually for a load/store), like: std r14,STK_REG(r14)(r1) Can't use STK_REG(r14) as %r14 doesn't work in the STK_REG macro since it's just calculating an offset. Signed-off-by:
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Michael Neuling authored
The assembler doesn't take %r0 register arguments in braces, so remove them. Signed-off-by:
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