- 21 Oct, 2023 11 commits
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Stephan Gerhold authored
Fix a couple of instances of incorrectly sorted nodes in the MSM8916 boards. They should be ordered alphabetically for consistency. No functional change. Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20230921-msm8916-rmem-fixups-v1-3-34d2b6e721cf@gerhold.netSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Stephan Gerhold authored
Enable &wcnss_mem for msm8939-longcheer-l9100. This is needed now to have WCNSS working. It was missed when &wcnss_mem was disabled by default because the patch with the msm8939-longcheer-l9100 device tree was not applied yet. Fixes: 0ece6438 ("arm64: dts: qcom: msm8916/39: Disable unneeded firmware reservations") Signed-off-by:
André Apitzsch <git@apitzsch.eu> Tested-by:
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Stephan Gerhold authored
Enable the GPU for the msm8916-samsung-gt58 and gt510 tablets now that they have display panels enabled in the device tree. This was missed when the GPU was disabled by default because the change was not applied yet. Fixes: 0ce5bb82 ("arm64: dts: qcom: msm8916/39: Disable GPU by default") Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-11-c8ceb1a37680@quicinc.com [bjorn: Updated commit message, as requested by Kathiravan] Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
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Kathiravan Thirumoorthy authored
While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by:
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Varadarajan Narayanan authored
IPQ95xx SoCs have different OPPs available for the CPU based on SoC variant. This can be determined from an eFuse register present in the silicon. Add support to read the eFuse and populate the OPPs based on it. Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw Limit ------------------------------------------------------------ 936000000 1 1 1 1 0xf 1104000000 1 1 1 1 0xf 1200000000 1 1 1 1 0xf 1416000000 0 1 1 1 0x7 1488000000 0 1 1 1 0x7 1800000000 0 1 0 1 0x5 2208000000 0 0 0 1 0x1 ----------------------------------------------------------- Reviewed-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.comSigned-off-by:
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Varadarajan Narayanan authored
IPQ53xx have different OPPs available for the CPU based on SoC variant. This can be determined through use of an eFuse register present in the silicon. Add support to read the eFuse and populate the OPPs based on it. ------------------------------------------------ Frequency BIT2 BIT1 opp-supported-hw 1.1GHz 1.5GHz ------------------------------------------------ 1100000000 1 1 0x7 1500000000 0 1 0x3 ------------------------------------------------ Signed-off-by:
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Richard Acayan authored
The bindings for the CPU frequency scaling driver require a specific compatible for the SoC. Add the compatible. Fixes: 0c665213 ("arm64: dts: qcom: sdm670: add cpu frequency scaling") Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Reviewed-by:
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Dmitry Baryshkov authored
Follow the example of other platforms and extend the PDC resource region to 0x30000, so that the PDC driver can read the PDC_VERSION register. Fixes: 397ad946 ("arm64: dts: qcom: sm8150: Add pdc interrupt controller node") Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230929-topic-sm8x50-upstream-pdc-ver-v5-2-800111572104@linaro.orgSigned-off-by:
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- 16 Oct, 2023 17 commits
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Robert Marko authored
Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018. Signed-off-by:
Robert Marko <robimarko@gmail.com> Reviewed-by:
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Caleb Connolly authored
The rb2 only has a single USB controller, it can be switched between a type-c port and an internal USB hub via a DIP switch. Until dynamic role switching is available it's preferable to put the USB controller in host mode so that the type-A ports and ethernet are available. Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Fixes: eaa53a85 ("arm64: dts: qcom: qrb4210-rb2: Enable USB node") Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231010-caleb-rb2-host-mode-v1-1-b057d443cd62@linaro.orgSigned-off-by:
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Priyansh Jain authored
Add tsens and thermal devicetree node for sa8775p SoC. Signed-off-by:
Priyansh Jain <quic_priyjain@quicinc.com> Link: https://lore.kernel.org/r/20230926085948.23046-3-quic_priyjain@quicinc.comSigned-off-by:
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Raghavendra Kakarla authored
Add device node for sleep stats driver which provides various low power mode stats. Tested-by:
Andrew Halaney <ahalaney@redhat.com> Signed-off-by:
Raghavendra Kakarla <quic_rkakarla@quicinc.com> Reviewed-by:
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Luca Weiss authored
Add the USB3+DP Combo QMP PHY port subnodes to facilitate the description of the connection between the hardware blocks. Put it in the SoC DTSI to avoid duplication in the device DTs. Reviewed-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20230929-sc7280-qmpphy-ports-v2-1-aae7e9c286b0@fairphone.comSigned-off-by:
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Konrad Dybcio authored
To make dtbs_check happy and the software more aware of what's going on, describe the HSUSB PHY's regulators and tighten up VDDA_PLL to match. Signed-off-by:
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Konrad Dybcio authored
Enable the onboard QCA Wi-Fi. HW identifiers for reference: qmi chip_id 0x320 chip_family 0x4001 board_id 0xff soc_id 0x400e0000 Firmware sources: /vendor/firmware_mnt/image/wlanmdsp.bin -> qcom/.../wlanmdsp.mbn /vendor/firmware_mnt/image/bdwlan.bXX [1] -> [2] -> ath10k/.../board-2.bin [3] -> ath10k/.../firmware-5.bin Not sure where 3 comes from on the device itself, gotta investigate that.. According to [4], it's called WCN3990_STRAIT. Enable it and tighten the relevant regulators. [1] XX = board_id printed when the file is missing or by your downstream kernel firmware loader in the dmesg; if XX=ff, use bdwlan.bin [2] https://github.com/jhugo/linux/blob/5.5rc2_wifi/README [3] https://github.com/kvalo/ath10k-firmware/blob/master/WCN3990/hw1.0/HL3.1/WLAN.HL.3.1-01040-QCAHLSWMTPLZ-1/firmware-5.bin [4] https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/qca-wifi-host-cmn/-/blob/LA.VENDOR.1.0.r1-20700-WAIPIO.QSSI13.0/hif/src/hif_hw_version.h#L55Signed-off-by: -
Konrad Dybcio authored
Enable the 5G modem on the Sony Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Add UART1 node, generally used for the Bluetooth module. Signed-off-by:
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Anusha Rao authored
Add support for wps buttons on GPIO 37. Reviewed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
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Anusha Rao authored
Add a dtsi file to include interfaces that are common across RDPs. Signed-off-by:
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Nitheesh Sekar authored
Enable USB2 in host mode. Reviewed-by:
Amandeep Singh <quic_amansing@quicinc.com> Signed-off-by:
Nitheesh Sekar <quic_nsekar@quicinc.com> Link: https://lore.kernel.org/r/20230904063635.24975-5-quic_nsekar@quicinc.comSigned-off-by:
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Nitheesh Sekar authored
Add USB phy and controller nodes. Co-developed-by:
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Om Prakash Singh authored
The sc7280 SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by:
Om Prakash Singh <quic_omprsing@quicinc.com> Link: https://lore.kernel.org/r/20231015193901.2344590-5-quic_omprsing@quicinc.com [bjorn: Padded address to 8 digits, moved hunk to maintain sort order] Signed-off-by:
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Om Prakash Singh authored
The sa8775p SoC has a True Random Number Generator, add the node with the correct compatible set. Signed-off-by:
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Neil Armstrong authored
The SM8450 SoC has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20231003-topic-sm8550-rng-v4-5-255e4d0ba08e@linaro.orgSigned-off-by:
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Neil Armstrong authored
Add the Qualcomm True Random Number Generator node. Reviewed-by:
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- 27 Sep, 2023 1 commit
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Stephan Gerhold authored
Add the missing regulator supplies to the ADV7533 HDMI bridge to fix the following dtbs_check warnings. They are all also supplied by pm8916_l6 so there is no functional difference. apq8016-sbc.dtb: bridge@39: 'dvdd-supply' is a required property apq8016-sbc.dtb: bridge@39: 'pvdd-supply' is a required property apq8016-sbc.dtb: bridge@39: 'a2vdd-supply' is a required property from schema display/bridge/adi,adv7533.yaml Fixes: 28546b09 ("arm64: dts: apq8016-sbc: Add HDMI display support") Signed-off-by:
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- 23 Sep, 2023 1 commit
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Luca Weiss authored
Now that the pm7250b.dtsi can be configured to be on a different SID, we also need to specify it for this dts file. Set it to the SID 2/3 like it was before commit 8e2d56f6 ("arm64: dts: qcom: pm7250b: make SID configurable"). Fixes: 8e2d56f6 ("arm64: dts: qcom: pm7250b: make SID configurable") Signed-off-by:
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- 22 Sep, 2023 1 commit
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Vignesh Raman authored
Due to the presence of the fastboot micro cable in the CI farm, it causes the hardware to remain in gadget mode instead of host mode. So it doesn't find the network, which results in failure to mount root fs via NFS. Add an overlay dtso file that sets the dr_mode to host, allowing the USB controllers to work in host mode. With commit 15d16d6d ("kbuild: Add generic rule to apply fdtoverlay"), overlay target can be used to simplify the build of DTB overlays. It uses fdtoverlay to merge base device tree with the overlay dtso. apq8016-sbc-usb-host.dtb file can be used by drm-ci, mesa-ci. Suggested-by:
Maxime Ripard <mripard@kernel.org> Signed-off-by:
Helen Koike <helen.koike@collabora.com> Signed-off-by:
David Heidelberg <david.heidelberg@collabora.com> Signed-off-by:
Vignesh Raman <vignesh.raman@collabora.com> Reviewed-by:
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- 20 Sep, 2023 9 commits
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Luca Weiss authored
Add device tree for the Fairphone 5 smartphone which is based on the QCM6490 SoC. Supported features are, as of now: * Bluetooth * Debug UART * Display via simplefb * Flash/torch LED * Flip cover sensor * Power & volume buttons * RTC * SD card * USB * Various plumbing like regulators, i2c, spi, etc Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230919-fp5-initial-v2-7-14bb7cedadf5@fairphone.comSigned-off-by:
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Luca Weiss authored
Fairphone 5 is a smartphone based on the QCM6490 SoC. Signed-off-by:
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Luca Weiss authored
Add a node for the led controller found on PM8350C, used for flash and torch purposes. Signed-off-by:
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Luca Weiss authored
Like other Qualcomm PMICs the PM7250B can be used on different addresses on the SPMI bus. Use similar defines like the PMK8350 to make this possible but skip the ifndef based on maintainer feedback. Signed-off-by:
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Luca Weiss authored
With the standard Qualcomm TrustZone setup, components such as lpasscc, pdc_reset and watchdog shouldn't be touched by Linux. Mark them with the status 'reserved' and reenable them in the chrome-common dtsi. Signed-off-by:
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Gaurav Kohli authored
Fix the apps iommu local address space range as per data sheet. Fixes: 61550c6c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by:
Gaurav Kohli <quic_gkohli@quicinc.com> Reviewed-by:
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Robert Marko authored
Now that SCM has support for indicating that SDI has been enabled by default, lets set the property so SCM disables it during probing. Signed-off-by:
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Adam Skladowski authored
Update bits to match downstream irq-bitmask values. Fixes: 0484d3ce ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Link: https://lore.kernel.org/r/20230812112534.8610-8-a39.skl@gmail.comSigned-off-by:
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Adam Skladowski authored
MSM8976 downstream dts define reloc region which is used by pil-tz to load both wcnss and lpass, on mainline however we might not be able to do it and we need separate regions(also validating dts might get problematic if we had to put memory-region(rproc node) per device). Luckily it seems size and entry points in firmware headers appears to be static across multiple devices including Sony Loire platform and Xiaomi Redmi Note 3 Pro this should let us fit in first ~17MB Split lpass region(reloc on downstream) into two separate regions. Signed-off-by:
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