1. 08 May, 2015 32 commits
    • Mika Kuoppala's avatar
      drm/i915: Free wa_batchbuffer when freeing error state · b3da4a62
      Mika Kuoppala authored
      wa_batchbuffer is part of some error states. Make sure it
      is freed.
      Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b3da4a62
    • Jani Nikula's avatar
      drm/i915/audio: do not mess with audio registers if port is invalid · d3902c3e
      Jani Nikula authored
      We should no longer enter the codec enable/disable functions in question
      with port A anyway, but to err on the safe side, keep the warnings. Just
      bail out early without messing with the registers.
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Reviewed-by: default avatarSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d3902c3e
    • Damien Lespiau's avatar
      drm/i915/skl: Make the Misc I/O power well part of the PLLS domain · 6222709d
      Damien Lespiau authored
      The specs tell us to ungate PG1 and Misc I/O at display init. We'll use
      the PLLS power domain to ensure those two power wells are up.
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      6222709d
    • Damien Lespiau's avatar
    • Damien Lespiau's avatar
      drm/i915: Re-order the PCU opcodes · 9043ae02
      Damien Lespiau authored
      Let's keep that list sorted!
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9043ae02
    • Damien Lespiau's avatar
    • Damien Lespiau's avatar
    • Michel Thierry's avatar
      drm/i915: Fix 32b overflow check in gen8_ppgtt_alloc_page_directories · 4dd738e9
      Michel Thierry authored
      The patch 69876bed: "drm/i915/gen8:
      page directories rework allocation" added an overflow warning, but the
      mask had an extra 0. Use less typo-prone option suggested by Dave
      instead, to check for (start + length) >= 0x100000000ULL.
      
      This check will be unnecessary after gen8_alloc_va_range handles more
      than 4 PDPs (48b addressing).
      
      v2: Really check for 32b overflow (Ville)
      Reported-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
      Cc: Dave Gordon <david.s.gordon@intel.com>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarMichel Thierry <michel.thierry@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4dd738e9
    • Mika Kuoppala's avatar
      drm/i915: Clear vma->bound on unbinding · 5e562f1d
      Mika Kuoppala authored
      Unbinding doesn't always lead to unconditional destruction
      of vma. This destruction avoidance happens if vma is part of
      execbuffer relocation list or if vma is being considered for
      eviction in i915_gem_evict_something().
      
      For those other users, mark the vma unbound so that
      the correct state of this vma is preserved.
      Reported-by: default avatarChris Wilson <chris@chris-wilson.co.ok>
      Cc: Chris Wilson <chris@chris-wilson.co.ok>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      5e562f1d
    • Jani Nikula's avatar
      drm/i915: make drm_crtc_helper_funcs const data · 65b38e0d
      Jani Nikula authored
      Because they can be.
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      65b38e0d
    • Mika Kahola's avatar
      drm/i915: DP link training optimization · 5fa836a9
      Mika Kahola authored
      This patch adds DP link training optimization by reusing the
      previously trained values.
      
      v2:
      - rebase
      
      V3:
      - rebase
      
      V4:
      - when HPD long pulse is received, the flag is cleared
        that indicates if DP link training is required or not
        (based on Sivakumar's comment)
      Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
      Reviewed-by: default avatarSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      5fa836a9
    • Mika Kahola's avatar
      drm/i915: eDP link training optimization · 4e96c977
      Mika Kahola authored
      This is a first of series patches that optimize DP link
      training. The first patch is for eDP only where we reuse
      the previously trained link training values from cache
      i.e. voltage swing and pre-emphasis levels.
      
      In case we are not able to train the link by reusing
      the known values, the link training parameters are set
      to zero and training is restarted.
      
      V2:
      - flag that indicates if DP link is trained and valid
        renamed from 'link_trained' to 'train_set_valid'
      - removed routine 'intel_dp_reuse_link_train'
      
      V3:
      - rebased against the latest drm-intel-nightly
      
      V4:
      - removed HPD long pulse handling for eDP case to clear the
        flag that indicates to reuse the current link training
        parameters. (based on Sivakumar's comment)
      Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
      Reviewed-by: default avatarSivakumar Thulasimani <sivakumar.thulasimani@intel.com>
      [danvet: s/DP/eDP/ in subject to make scope clear.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      4e96c977
    • Deepak S's avatar
      drm/i915: Setup static bias for GPU · 3ef62342
      Deepak S authored
      Based on the spec, Setting up static BIAS for GPU to improve the
      rps performace.
      
      v2: rename reg defn to match spec. (Ville)
      
      v3: Updated bias setting for chv (Deepak)
      Signed-off-by: default avatarDeepak S <deepak.s@linux.intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      3ef62342
    • Dan Carpenter's avatar
      drm/i915: checking IS_ERR() instead of NULL · 3126a660
      Dan Carpenter authored
      We switched from calling i915_gem_alloc_context_obj() to calling
      i915_gem_alloc_object() so the error handling needs to be updated to
      check for NULL instead of IS_ERR().
      
      Fixes: 149c86e7 ('drm/i915: Allocate context objects from stolen')
      Signed-off-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      3126a660
    • Chris Wilson's avatar
      drm/i915: Remove incorrect restriction on 32bit offsets in ppGTT backend · d4dc5e92
      Chris Wilson authored
      This is the wrong layer to apply an arbitrary restriction and the wrong
      error code (object too large!). If we do want to prevent large offsets
      being return to the user on 32bit systems (to hide bugs in userspace),
      you want to restrict the drm_mm range manager instead. This first tells
      userspace about the correct size of the GTT they can use (so they don't
      try and overallocate object or batches), and fixes the eviction logic to
      avoid the eventual and *guaranteed* error.
      
      Fixes regression in
      commit d7b2633d
      Author: Michel Thierry <michel.thierry@intel.com>
      Date:   Wed Apr 8 12:13:34 2015 +0100
      
          drm/i915/gen8: Dynamic page table allocations
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d4dc5e92
    • Chris Wilson's avatar
      drm/i915: Add RPS thresholds to debugfs/i915_frequency_info · d86ed34a
      Chris Wilson authored
      Expose some more of our internal RPS bookkeeping for debugging.
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      d86ed34a
    • Fabian Frederick's avatar
      drm/i915: use ERR_CAST instead of ERR_PTR/PTR_ERR · 0b6cc188
      Fabian Frederick authored
      Inspired by scripts/coccinelle/api/err_cast.cocci
      Signed-off-by: default avatarFabian Frederick <fabf@skynet.be>
      Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      0b6cc188
    • Joonas Lahtinen's avatar
      drm/i915: Do not clear mappings beyond VMA size · 06615ee5
      Joonas Lahtinen authored
      Do not to clear mappings outside the allocated VMA under any
      circumstances. Only clear the smaller of VMA or object page count.
      
      This is required to allow creating partial object VMAs which in
      turn are needed for partial GGTT views.
      Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      06615ee5
    • Todd Previte's avatar
      drm/i915: Move Displayport test request and sink IRQ logic to intel_dp_detect() · 09b1eb13
      Todd Previte authored
      Due to changes in the driver and to support Displayport compliance testing,
      the test request and sink IRQ logic has been relocated from
      intel_dp_check_link_status to intel_dp_detect. This is because the bulk of the
      compliance tests that set the TEST_REQUEST bit in the DEVICE_IRQ field of the
      DPCD issue a long pulse / hot plug event to signify the start of the test.
      Currently, for a long pulse, intel_dp_check_link_status is not called for a
      long HPD pulse, so if test requests come in, they cannot be detected by the
      driver.
      
      Once located in the intel_dp_detect, in the regular hot plug event path,
      proper detection of Displayport compliance test requests occurs which then
      invokes the test handler to support them. Additionally, this places compliance
      testing in the normal operational paths, eliminating as much special case code
      as possible.
      
      The only change in intel_dp_check_link_status with this patch is that when
      the IRQ is the result of a test request from the sink, the test handler is not
      invoked during the short pulse path. Short pulse test requests are for a
      particular variety of tests (mainly link training) that will be implemented
      in the future. Once those tests are available, the test request handler will
      be called from here as well.
      
      V2:
      - Rewored the commit message to be more clear about the content and intent
        of this patch
      - Restore IRQ detection logic to intel_dp_check_link_status(). Continue to
        detect and clear sink IRQs in the short pulse case. Ignore test requests
        in the short pulses for now since they are for future test implementations.
      Signed-off-by: default avatarTodd Previte <tprevite@gmail.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      09b1eb13
    • Suketu Shah's avatar
      drm/i915/skl: Enable runtime PM · 00776511
      Suketu Shah authored
      Enable runtime PM for Skylake platform
      
      v2: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      00776511
    • Suketu Shah's avatar
      drm/i915/skl: Assert the requirements to enter or exit DC6. · 93c7cb6c
      Suketu Shah authored
      Warn if the conditions to enter or exit DC6 are not satisfied such
      as support for runtime PM, state of power well, CSR loading etc.
      
      v2: Removed camelcase in functions and variables.
      
      v3: Do some minimal check to assert if CSR program is not loaded.
      
      v4:
      1] Correct the check for backlight-disabling in assert_can_enable_dc6().
      2] Check csr.loaded = false before disabling DC6 and simplify other checks.
      
      v5:
      1] Remove checks for DC5 state from assert_can_enable_dc6 function as DC5 is no
         longer enabled before enabling DC6.
      2] Correct the check for CSR-loading in assert_can_disable_dc6 function as CSR must
         be loaded for context restore to happen on DC6 disabling.
      
      v6:
      1] It's okay to explicitly disable DC6 during driver-load/resume even though it might
         already be disabled and so don't warn about it.
      
      v7: Rebase to latest.
      
      v8: Sqashed the patch from Imre -
      [PATCH] drm/i915/skl: avoid false CSR fw not loaded WARN during driver load/resume
      
      v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
      
      v10: During initialization added a early return before disabling DC5. (Animesh)
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      93c7cb6c
    • A.Sunil Kamath's avatar
      Implement enable/disable for Display C6 state · 74b4f371
      A.Sunil Kamath authored
      This patch just implements the basic enable and disable
      functions of DC6 state which is needed for SKL platform.
      
      Its important to load SKL CSR program before calling enable.
      
      DC6 is a deeper power saving state where hardware dynamically
      disables power well 0 and saves the associated registers.
      DC6 can be entered when software allows it, the conditions
      for DC5 are met, and the PCU allows DC6.
      DC6 cannot be used if the backlight is being driven from the
      display utility pin.
      
      Its better to configure display engine to have power well 2
      disabled before getting into DC6 enable function. Hence rpm
      framework will ensure to check status of power well 2 and DC5
      before calling skl_enable_dc6.
      
      v2: Replace HAS_ with IS_ check as per Daniel's review comments
      
      v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register
      before setting them as per Satheesh's review comments.
      
      v4: No need to call gen9_disable_dc5 inside enable sequence of
      DC6, as its already take care above.
      
      v5: call POSTING_READ for every write to a register to ensure that
      its written immediately.
      Call intel_prepare_ddi during DC6 exit as it's required on low-power exit.
      
      v6: Protect DC6-enabling-disabling functionality with locks to synchronize
      with CSR-loading code.
      
      v7: Remove grabbing CSR-related mutex in skl_enable/disable_dc6 functions as
          deferred DC5-enabling functionality is now removed.
      
      v8: Remove 'Disabling DC5' from the debug comment during DC6 enabling as when
          DC6 is allowed, DC5 is not programmed at all.
      
      v9:
      - Rebase to latest.
      - Move all DC6-related functions from intel_display.c to intel_runtime_pm.c.
      
      v10: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      74b4f371
    • Suketu Shah's avatar
      drm/i915/skl: Add DC6 Trigger sequence. · f75a1985
      Suketu Shah authored
      Add triggers for DC6 as per details provided in skl_enable_dc6
      and skl_disable_dc6 implementations.
      
      Also Call POSTING_READ for every write to a register to ensure
      it is written to immediately
      
      v1: Remove POSTING_READ and intel_prepare_ddi calls as they've been added in previous patches.
      
      v2:
      1] Remove check for backlight disabled as it should be the case by that time.
      2] Mark DC5 as disabled when enabling DC6.
      3] Return from DC5-disabling function early if DC5 is already be disabled which can happen
         due to DC6-enabling earlier.
      3] Ensure CSR firmware is loaded after resume from DC6 as corresponding memory contents won't
         be retained after runtime-suspend.
      4] Ensure that CSR isn't identified as loaded before CSR-loading program is called during
         runtime-resume.
      
      v3: Rebase to latest
      Modified as per review comments from Imre and after discussion with Art:
      1] DC6 should be preferably enabled when PG2 is disabled by SW as the check for PG1 being
         disabled is taken of by HW to enter DC6, and disabled when PG2 is enabled respectively.
         This helps save more power, especially in the case when display is disabled but GT is
         enabled. Accordingly, replacing DC5 trigger sequence with DC6 for SKL.
      2] DC6 could be enabled from intel_runtime_suspend() function, if DC5 is already enabled.
      3] Move CSR-load-status setting code from intel_runtime_suspend function to a new function.
      
      v4:
      1] Enable/disable DC6 only when toggling the power-well using a newly defined macro ENABLE_DC6.
      
      v5:
      1] Load CSR on system resume too as firmware may be lost on system suspend preventing
         enabling DC5, DC6.
      2] DDI buffers shouldn't be programmed during driver-load/resume as it's already done
         during modeset initialization then and also that the encoder list is still uninitialized by
         then. Therefore, call intel_prepare_ddi function right after disabling DC6 but outside
         skl_disable_dc6 function and not during driver-load/resume.
      
      v6:
      1] Rebase to latest.
      2] Move SKL_ENABLE_DC6 macro definition from intel_display.c to intel_runtime_pm.c.
      
      v7:
      1) Refactored the code for removing the warning got from checkpatch.
      2) After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
      
      v8:
      - Reverted the changes done in v7.
      - Removed the condition check in skl_prepare_resune(). (Animesh)
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      f75a1985
    • Suketu Shah's avatar
      drm/i915/skl: Assert the requirements to enter or exit DC5. · 5aefb239
      Suketu Shah authored
      Warn if the conditions to enter or exit DC5 are not satisfied such
      as support for runtime PM, state of power well, CSR loading etc.
      
      v2: Removed camelcase in functions and variables.
      
      v3: Do some minimal check to assert if CSR program is not loaded.
      
      v4:
      1] Used an appropriate function lookup_power_well() to identify power well,
      instead of using a magic number which can change in future.
      2] Split the conditions further in assert_can_enable_DC5() and added more checks.
      3] Removed all WARNs from assert_can_disable_DC5 as they were unnecessary and added two
         new ones.
      4] Changed variable names as updated in earlier patches.
      
      v5:
      1] Change lookup_power_well function to take an int power well id.
      2] Define a new intel_display_power_well_is_enabled helper function to check whether a
         particular power well is enabled.
      3] Use CSR-related mutex in assert_csr_loaded function.
      
      v6: Remove use of dc5_enabled variable as it's no longer needed.
      
      v7:
      1] Rebase to latest.
      2] Move all DC5-related functions from intel_display.c to intel_runtime_pm.c.
      
      v8: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
      
      v9: Modified below changes based on review comments from Imre.
      - Moved intel_display_power_well_is_enabled() to intel_runtime_pm.c.
      - Removed mutex lock from assert_csr_loaded(). (Animesh)
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      5aefb239
    • A.Sunil Kamath's avatar
      drm/i915/skl: Implement enable/disable for Display C5 state. · 6b457d31
      A.Sunil Kamath authored
      This patch just implements the basic enable and disable
      functions of DC5 state which is needed for both SKL and BXT.
      
      Its important to load respective CSR program before calling
      enable, which anyways will happen as CSR program is executed
      during boot.
      
      DC5 is a power saving state where hardware dynamically disables
      power well 1 and the CDCLK PLL and saves the associated registers.
      
      DC5 can be entered when software allows it, power well 2 is
      disabled, and hardware detects that all pipes are disabled
      or pipe A is enabled with PSR active.
      
      Its better to configure display engine to have power well 2 disabled before
      getting into DC5 enable function. Hence rpm framework will have to
      ensure to check status of power well 2 before calling gen9_enable_dc5.
      
      Rather dc5 entry criteria should be decided based on power well 2 status.
      If disabled, then call gen9_enable_dc5.
      
      v2: Replace HAS_ with IS_ check as per Daniel's review comments
      
      v3: Cleared the bits dc5/dc6 enable of DC_STATE_EN register
      before setting them as per Satheesh's review comments.
      
      v4: call POSTING_READ for every write to a register to ensure that
      its written immediately.
      
      v5: Modified as per review comments from Imre.
      - Squashed register definitions into this patch.
      - Finetuned comments and functions.
      
      v6:
      Avoid redundant writes in gen9_set_dc_state_debugmask_memory_up function.
      
      v7:
      - Rebase to latest.
      - Move all runtime PM functions defined in intel_display.c to
        intel_runtime_pm.c.
      
      v8: Rebased to drm-intel-nightly. (Animesh)
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      6b457d31
    • Suketu Shah's avatar
      drm/i915/skl: Add DC5 Trigger Sequence · dc174300
      Suketu Shah authored
      Add triggers as per expectations mentioned in gen9_enable_dc5
      and gen9_disable_dc5 patch.
      
      Also call POSTING_READ for every write to a register to ensure that
      its written immediately.
      
      v1: Remove POSTING_READ calls as they've already been added in previous patches.
      
      v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
      
      Modified as per review comments from Imre:
      1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
         functions.
      2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
         gen9_disable_DC5 which is a more appropriate place.
      3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
         to warnings. However, removing them for now as they'll be included in a future patch
         asserting DC-state entry/exit criteria.
      4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
         to track 'enabled' and 'deferred' status of DC5.
      5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
         runtime-suspend and release it when it's loaded.
      6] Protect necessary CSR-related code with locks.
      7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
         accessed during deferred DC5-enabling, are not initialized earlier.
      
      v3: Rebase to latest.
      
      Modified as per review comments from Imre:
      1] Use blocking wait for CSR-loading to finish to enable DC5  for simplicity, instead of
         deferring enabling DC5 until CSR is loaded.
      2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
         enabling is removed and release it at the end of CSR-loading functionality.
      3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
         functionality to avoid any delay in loading.
      4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
         DC5 if it's true.
      5] Define CSR-load-status accessor functions for use later.
      
      v4:
      1] Disable DC5 before enabling PG2 instead of after it.
      2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
      3] Enable DC5-related functionality using a macro.
      4] Remove dc5_enabled tracking variable and its use as it's not needed now.
      
      v5:
      1] Mark CSR failed to load where necessary in finish_csr_load function.
      2] Use mutex-protected accessor function to check if CSR loaded instead of directly
         accessing the variable.
      3] Prefix csr_load_status_get/set function names with intel_.
      
      v6: rebase to latest.
      v7: Rebase on top of nightly (Damien)
      v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
      v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
      v10: Added a enum for different csr states, suggested by Imre. (Animesh)
      
      v11: Based on review comments from Imre, Damien and Daniel following changes done
      - enum name chnaged to csr_state (singular form).
      - FW_UNINITIALIZED used as zeroth element in enum csr_state.
      - Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
      
      v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
      calling once to set the csr status. The same flag used to fail RPM if find any issue during
      firmware loading.
      
      Issue: VIZ-2819
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarSuketu Shah <suketu.j.shah@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      dc174300
    • Daniel Vetter's avatar
      drm/i915/skl: Add support to load SKL CSR firmware. · eb805623
      Daniel Vetter authored
      Display Context Save and Restore support is needed for
      various SKL Display C states like DC5, DC6.
      
      This implementation is added based on first version of DMC CSR program
      that we received from h/w team.
      
      Here we are using request_firmware based design.
      Finally this firmware should end up in linux-firmware tree.
      
      For SKL platform its mandatory to ensure that we load this
      csr program before enabling DC states like DC5/DC6.
      
      As CSR program gets reset on various conditions, we should ensure
      to load it during boot and in future change to be added to load
      this system resume sequence too.
      
      v1: Initial relese as RFC patch
      
      v2: Design change as per Daniel, Damien and Shobit's review comments
      request firmware method followed.
      
      v3: Some optimization and functional changes.
      Pulled register defines into drivers/gpu/drm/i915/i915_reg.h
      Used kmemdup to allocate and duplicate firmware content.
      Ensured to free allocated buffer.
      
      v4: Modified as per review comments from Satheesh and Daniel
      Removed temporary buffer.
      Optimized number of writes by replacing I915_WRITE with I915_WRITE64.
      
      v5:
      Modified as per review comemnts from Damien.
      - Changed name for functions and firmware.
      - Introduced HAS_CSR.
      - Reverted back previous change and used csr_buf with u8 size.
      - Using cpu_to_be64 for endianness change.
      
      Modified as per review comments from Imre.
      - Modified registers and macro names to be a bit closer to bspec terminology
      and the existing register naming in the driver.
      - Early return for non SKL platforms in intel_load_csr_program function.
      - Added locking around CSR program load function as it may be called
      concurrently during system/runtime resume.
      - Releasing the fw before loading the program for consistency
      - Handled error path during f/w load.
      
      v6: Modified as per review comments from Imre.
      - Corrected out_freecsr sequence.
      
      v7: Modified as per review comments from Imre.
      Fail loading fw if fw->size%8!=0.
      
      v8: Rebase to latest.
      
      v9: Rebase on top of -nightly (Damien)
      
      v10: Enabled support for dmc firmware ver 1.0.
      According to ver 1.0 in a single binary package all the firmware's that are
      required for different stepping's of the product will be stored. The package
      contains the css header, followed by the package header and the actual dmc
      firmwares. Package header contains the firmware/stepping mapping table and
      the corresponding firmware offsets to the individual binaries, within the
      package. Each individual program binary contains the header and the payload
      sections whose size is specified in the header section. This changes are done
      to extract the specific firmaware from the package. (Animesh)
      
      v11: Modified as per review comemnts from Imre.
      - Added code comment from bpec for header structure elements.
      - Added __packed to avoid structure padding.
      - Added helper functions for stepping and substepping info.
      - Added code comment for CSR_MAX_FW_SIZE.
      - Disabled BXT firmware loading, will be enabled with dmc 1.0 support.
      - Changed skl_stepping_info based on bspec, earlier used from config DB.
      - Removed duplicate call of cpu_to_be* from intel_csr_load_program function.
      - Used cpu_to_be32 instead of cpu_to_be64 as firmware binary in dword aligned.
      - Added sanity check for header length.
      - Added sanity check for mmio address got from firmware binary.
      - kmalloc done separately for dmc header and dmc firmware. (Animesh)
      
      v12: Modified as per review comemnts from Imre.
      - Corrected the typo error in skl stepping info structure.
      - Added out-of-bound access for skl_stepping_info.
      - Sanity check for mmio address modified.
      - Sanity check added for stepping and substeppig.
      - Modified the intel_dmc_info structure, cache only the required header info. (Animesh)
      
      v13: clarify firmware load error message.
      The reason for a firmware loading failure can be obscure if the driver
      is built-in. Provide an explanation to the user about the likely reason for
      the failure and how to resolve it. (Imre)
      
      v14: Suggested by Jani.
      - fix s/I915/CONFIG_DRM_I915/ typo
      - add fw_path to the firmware object instead of using a static ptr (Jani)
      
      v15:
      1) Changed the firmware name as dmc_gen9.bin, everytime for a new firmware version a symbolic link
      with same name will help not to build kernel again.
      2) Changes done as per review comments from Imre.
      - Error check removed for intel_csr_ucode_init.
      - Moved csr-specific data structure to intel_csr.h and optimization done on structure definition.
      - fw->data used directly for parsing the header info & memory allocation
      only done separately for payload. (Animesh)
      
      v16:
      - No need for out_regs label in i915_driver_load(), so removed it.
      - Changed the firmware name as skl_dmc_ver1.bin, followed naming convention <platform>_dmc_<api-version>.bin (Animesh)
      
      Issue: VIZ-2569
      Signed-off-by: default avatarA.Sunil Kamath <sunil.kamath@intel.com>
      Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
      Signed-off-by: default avatarAnimesh Manna <animesh.manna@intel.com>
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      eb805623
    • Daniel Vetter's avatar
      drm/i915: Simplify cmd-parser DISPATCH_SECURE check · c6b8a4bc
      Daniel Vetter authored
      i915_needs_cmd_parser already checks that for us.
      Suggested-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
      c6b8a4bc
    • Nick Hoath's avatar
    • Chandra Konduru's avatar
      drm/i915: skylake sprite plane scaling using shared scalers · c331879c
      Chandra Konduru authored
      This patch enables skylake sprite plane display scaling using shared
      scalers atomic desgin.
      
      v2:
      -use single copy of scaler limits (Matt)
      
      v3:
      -detaching scalers moved to crtc commit path (Matt)
      
      v4:
      -changes to align with updated scaler structures (Matt, me)
      -keep sprite src rect in 16.16 format (Matt, Daniel)
      
      v5:
      -rebased on top of 90/270 rotation changes (me)
      -Refactored skl_update_plane to reduce its size (Daniel)
       It is a step towards having a single function covering all planes.
      Signed-off-by: default avatarChandra Konduru <chandra.konduru@intel.com>
      Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
      Testcase: igt/kms_plane_scaling
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      c331879c
    • Chandra Konduru's avatar
      drm/i915: skylake primary plane scaling using shared scalers · 6156a456
      Chandra Konduru authored
      This patch enables skylake primary plane scaling using shared
      scalers atomic desgin.
      
      v2:
      -use single copy of scaler limits (Matt)
      
      v3:
      -move detach_scalers to crtc commit path (Matt)
      -use values in plane_state->src as regular integers (me)
      
      v4:
      -changes to align with updated scaler structures (Matt, me)
      -keep plane src rect in 16.16 format (Matt, Daniel)
      
      v5:
      -Rebased on top of 90/270 rotation changes (me)
      -Fixed an issue introduced by 90/270 changes where plane programming
       is using drm_plane->state rect instead of intel_plane->state rect.
       This change also required for scaling to work properly. (me)
      -With 90/270, updated limits to cover both portrait and landscape usages (me)
      -Refactored skylake_update_primary_plane to reduce its size (Daniel)
       Added helper functions for refactoring are comprehended enough to be
       used for skylake_update_plane (for sprite) too. One stop towards
       having single function for all planes.
      
      v6:
      -Added fixme note when checking plane_state->src width in update_plane (Daniel)
      -Release lock when failing to colorkey request with active scaler (Daniel)
      Signed-off-by: default avatarChandra Konduru <chandra.konduru@intel.com>
      Reviewed-by: matthew.d.roper@intel.com
      Reviewed-by: sonika.jindal@intel.com (v5)
      Testcase: igt/kms_plane_scaling
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      6156a456
    • Dave Airlie's avatar
      Merge tag 'drm-intel-next-2015-04-23-fixed' of... · e1dee197
      Dave Airlie authored
      Merge tag 'drm-intel-next-2015-04-23-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next
      
      drm-intel-next-2015-04-23:
      - dither support for ns2501 dvo (Thomas Richter)
      - some polish for the gtt code and fixes to finally enable the cmd parser on hsw
      - first pile of bxt stage 1 enabling (too many different people to list ...)
      - more psr fixes from Rodrigo
      - skl rotation support from Chandra
      - more atomic work from Ander and Matt
      - pile of cleanups and micro-ops for execlist from Chris
      drm-intel-next-2015-04-10:
      - cdclk handling cleanup and fixes from Ville
      - more prep patches for olr removal from John Harrison
      - gmbus pin naming rework from Jani (prep for bxt)
      - remove ->new_config from Ander (more atomic conversion work)
      - rps (boost) tuning and unification with byt/bsw from Chris
      - cmd parser batch bool tuning from Chris
      - gen8 dynamic pte allocation (Michel Thierry, based on work from Ben Widawsky)
      - execlist tuning (not yet all of it) from Chris
      - add drm_plane_from_index (Chandra)
      - various small things all over
      
      * tag 'drm-intel-next-2015-04-23-fixed' of git://anongit.freedesktop.org/drm-intel: (204 commits)
        drm/i915/gtt: Allocate va range only if vma is not bound
        drm/i915: Enable cmd parser to do secure batch promotion for aliasing ppgtt
        drm/i915: fix intel_prepare_ddi
        drm/i915: factor out ddi_get_encoder_port
        drm/i915/hdmi: check port in ibx_infoframe_enabled
        drm/i915/hdmi: fix vlv infoframe port check
        drm/i915: Silence compiler warning in dvo
        drm/i915: Update DRIVER_DATE to 20150423
        drm/i915: Enable dithering on NatSemi DVO2501 for Fujitsu S6010
        rm/i915: Move i915_get_ggtt_vma_pages into ggtt_bind_vma
        drm/i915: Don't try to outsmart gcc in i915_gem_gtt.c
        drm/i915: Unduplicate i915_ggtt_unbind/bind_vma
        drm/i915: Move ppgtt_bind/unbind around
        drm/i915: move i915_gem_restore_gtt_mappings around
        drm/i915: Fix up the vma aliasing ppgtt binding
        drm/i915: Remove misleading comment around bind_to_vm
        drm/i915: Don't use atomics for pg_dirty_rings
        drm/i915: Don't look at pg_dirty_rings for aliasing ppgtt
        drm/i915/skl: Support Y tiling in MMIO flips
        drm/i915: Fixup kerneldoc for struct intel_context
        ...
      
      Conflicts:
      	drivers/gpu/drm/i915/i915_drv.c
      e1dee197
  2. 07 May, 2015 2 commits
    • Gerd Hoffmann's avatar
      drm/qxl: rewrite framebuffer support · c0fe07aa
      Gerd Hoffmann authored
      Completely different approach:  Instead of encoding each and every
      framebuffer update as spice operation simply update the shadow
      framebuffer and maintain a dirty rectangle.  Also schedule a worker
      to push an update for the dirty rectangle as spice operation.  Usually
      a bunch of dirty rectangle updates are collected before the worker
      actually runs.
      
      What changes:  Updates get batched now.  Instead of sending tons of
      small updates a few large ones are sent.  When the same region is
      updated multiple times within a short timeframe (scrolling multiple
      lines for example) we send a single update only.  Spice server has an
      easier job now:  The dependency tree for display operations which spice
      server maintains for lazy rendering is alot smaller now.  Spice server's
      image compression probably works better too with the larger image blits.
      
      Net effect:  framebuffer console @ qxldrmfb is an order of magnitude
      faster now.
      Signed-off-by: default avatarGerd Hoffmann <kraxel@redhat.com>
      Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
      c0fe07aa
    • Dave Airlie's avatar
      Merge tag 'topic/drm-misc-2015-05-06' of git://anongit.freedesktop.org/drm-intel into drm-next · 49f89764
      Dave Airlie authored
      misc drm core patches.
      
      * tag 'topic/drm-misc-2015-05-06' of git://anongit.freedesktop.org/drm-intel:
        drm: simplify master cleanup
        drm: simplify authentication management
        drm: drop unused 'magicfree' list
        drm: fix a memleak on mutex failure path
        drm/atomic-helper: Really recover pre-atomic plane/cursor behavior
        drm/qxl: Fix qxl_noop_get_vblank_counter()
        drm: Zero out invalid vblank timestamp in drm_update_vblank_count. (v2)
        drm: Prevent invalid use of vblank_disable_immediate. (v2)
        drm/vblank: Fixup and document timestamp update/read barriers
        DRM: Don't re-poll connector for disconnect
        drm: Fix for DP CTS test 4.2.2.5 - I2C DEFER handling
        drm: Fix the 'native defer' message in drm_dp_i2c_do_msg()
        drm/atomic-helper: Don't call atomic_update_plane when it stays off
      49f89764
  3. 05 May, 2015 4 commits
  4. 04 May, 2015 2 commits