- 22 Mar, 2012 2 commits
-
-
Ben Skeggs authored
These are FIFO methods, it doesn't matter what subchannel is being used. Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
-
Ben Skeggs authored
There was once good reasons for wanting the drm to be able to use M2MF etc on user channels, but they're not relevant anymore. For the general buffer move case, we've already lost by transferring between vram/sysmem already so the context switching overhead is minimal in comparison. Signed-off-by:
-
- 13 Mar, 2012 38 commits
-
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
NVIDIA appear to do these around the same place they do the MODE_CTRL methods, and for DP at least we need to bash some extra bits in "syncs" to keep EVO happy. It's a bit of a guess as to the 6/8bpc, but i have no better idea yet. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
GF119 will use this too. Signed-off-by: -
Martin Peres authored
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by:
Martin Peres <martin.peres@labri.fr> Signed-off-by:
-
Ben Skeggs authored
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: -
Ben Skeggs authored
More code to do the same thing, but will make it easier to handle various changes that could possibly happen the the VBIOS tables. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Refactored to allow shadowing of VBIOS images longer than 64KiB, which allows us to pass the VBIOS checksum test on certain boards. There's also a workaround for reading the PROM VBIOS on some chipsets. Signed-off-by: -
Ben Skeggs authored
There's cards out there with completely messed up PCIROM images that have a perfectly valid signature.. Sigh! Signed-off-by: -
Ben Skeggs authored
Theoretically handles CRTC2/CRTC3, should any GF119 out there actually have them enabled. The room is there for the regs etc, so why not :) Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Roy Spliet authored
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by:
Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by:
-
Ben Skeggs authored
Fixes reclocking failure on some chips where we attempted to set PDAEMON to PLL mode. Signed-off-by: -
Xi Wang authored
The comparison (lpre == DP_TRAIN_PRE_EMPHASIS_9_5) is always false: lpre is initialized as (lane & 0x0c) >> 2, which is at most 3, while DP_TRAIN_PRE_EMPHASIS_9_5 is defined as (3 << 3). Signed-off-by:
Xi Wang <xi.wang@gmail.com> Signed-off-by:
-
Ben Skeggs authored
There's a HP laptop out there where the MXM version in the VBIOS doesn't match what the ACPI implementation is expecting. These tables will accept 0x00 to MXMS to return latest version, but *only* if MXMI has been called first.. Signed-off-by: -
Ben Skeggs authored
This patch fixes an oops cause by pm_trigger accessing the (uninitialised) crtc list. Reported-by:
-
Ben Skeggs authored
Signed-off-by: -
Christoph Bumiller authored
Signed-off-by:
Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by:
-
Ben Skeggs authored
v2 (Emil Velikov <emil.l.velikov@gmail.com>): - Fixed a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Signed-off-by:
Emil Velikov <emil.l.velikov@gmail.com> Tested-by:
Johannes Obermayr <johannesobermayr@gmx.de>
-
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
Ben Skeggs authored
Fixes minor flickering on NVS295 when at perflvl 0. Signed-off-by:
-
Ben Skeggs authored
Goes a long way to correcting NVS295 memory reclocking issues. Signed-off-by:
-
Ben Skeggs authored
There's some "extended" GDDR3 chipsets out there with EMRS2 settings that change the layout of MRS/EMRS1 bitmaps.. Sigh.. Still need to track down how exactly we're supposed to handle this. Signed-off-by:
-
Martin Peres authored
Signed-off-by:
-
Ben Skeggs authored
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
Ben Skeggs authored
This will probably result in more lines of code, however, we're going to have at least 3 slightly different implementations of this very soon and I'd rather keep the ram reclocking logic separate from the hw specifics. DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary. Signed-off-by:
-
Ben Skeggs authored
Signed-off-by:
-
