- 29 May, 2024 13 commits
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Aurabindo Pillai authored
Drop the extra HPD irq entry for DCN401. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
Most of the DML code is generated, and it is necessary to update some parts of it from time to time. This commit brings the latest generated code for DML 2.1. Signed-off-by:
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Pinninti authored
[why] cleaning up the code refactor requires hubp to be in its own component. [how] move all files under newly created hubp folder and fixing the makefiles. Reviewed-by:
Pinninti <bpinnint@amd.com> Acked-by:
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Rodrigo Siqueira authored
This commit removes some unused code with the required adjustments. Signed-off-by:
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Samson Tam authored
[Why] Enable sharpener support for DCN401 [How] - Removed memcmp check that was preventing ISHARP from being enabled. - Add missing ISHARP register defines, masks, and writes. - Add programming of Blur and Scale coefficients. - Program FMT_MODE and NLDELTA registers based on LLS_PREF and pixel - format - Only enable ISHARP for YUV420 - Add disabling of ISHARP - Add debug flags and registry keys for debugging ISHARP. - Set default to medium level Acked-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Sridevi authored
[Why] Incorrect cursor position calculation in some scenarios. Also for mirror and rotation cases. [How] Fix for incorrect cursor position. Added new test scenarios for diags cursor test. Updated CRC for few of the diags cursor test scenarios. Reviewed-by:
Sridevi <sarvinde@amd.com> Acked-by:
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Yang Wang authored
fix typo "info.ue_count" in amdgpu_ras_aca_sysfs_read() function. Fixes: 865d3397 ("drm/amdgpu: add aca deferred error type support") Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Jesse Zhang authored
The pointer parent may be NULLed by the function amdgpu_vm_pt_parent. To make the code more robust, check the pointer parent. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Suggested-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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David (Ming Qiang) Wu authored
AMD_PG_SUPPORT_VCN_DPG is needed for secure parts and should/can be enabled by now. Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Reviewed-by:
Sonny Jiang <sonjiang@amd.com> Signed-off-by:
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Alex Deucher authored
It was an enablement vehicle for MES 11 and was never productized. Remove it. v2: drop additional checks in the GFX10 code. v3: drop mes_api_def.h Acked-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Jiapeng Chong authored
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5200 dc_power_down_on_boot() warn: inconsistent indenting. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9166Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Convert a variable sized array from [1] to []. Reviewed-by:
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Alex Deucher authored
Use current speed/width on devices which don't support dynamic PCIe switching. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3289Acked-by:
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- 23 May, 2024 27 commits
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Mario Limonciello authored
MST colorspace property support was disabled due to a series of warnings that came up when the device was plugged in since the properties weren't made at device creation. Create the properties in advance instead. Suggested-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Fixes: 69a95961 ("drm/amd/display: Temporary Disable MST DP Colorspace Property"). Reported-and-tested-by:
Tyler Schneider <tyler.schneider@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3353Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
The fix involves adding a null check for 'stream' at the beginning of the function. If 'stream' is NULL, the function immediately returns false. This ensures that 'stream' is not NULL when we dereference it to access 'ctx' in 'dc = stream->ctx->dc;' the function. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c:398 dc_stream_program_cursor_position() error: we previously assumed 'stream' could be null (see line 397) drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_stream.c 389 bool dc_stream_program_cursor_position( 390 struct dc_stream_state *stream, 391 const struct dc_cursor_position *position) 392 { 393 struct dc *dc; 394 bool reset_idle_optimizations = false; 395 const struct dc_cursor_position *old_position; 396 397 old_position = stream ? &stream->cursor_position : NULL; ^^^^^^^^ The patch adds a NULL check --> 398 dc = stream->ctx->dc; ^^^^^^^^ The old code didn't check 399 400 if (dc_stream_set_cursor_position(stream, position)) { 401 dc_z10_restore(dc); 402 403 /* disable idle optimizations if enabling cursor */ 404 if (dc->idle_optimizations_allowed && 405 (!old_position->enable || dc->debug.exit_idle_opt_for_cursor_updates) && 406 position->enable) { 407 dc_allow_idle_optimizations(dc, false); Fixes: f63f86b5 ("drm/amd/display: Separate setting and programming of cursor") Reported-by:Dan Carpenter <dan.carpenter@linaro.org> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Sunil Khatri authored
Add support of all the CP GFX queues for gfx11 ipdump to be used by devcoredump. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Sunil Khatri authored
Add gfx11 support of CP queue registers for all queues to be used by devcoredump. Reviewed-by:
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Mario Limonciello authored
Errors in amdgpu_dm_init() are silently ignored and dm_hw_init() will succeed. However often these are fatal errors and it would be better to pass them up. Reviewed-by:
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Sunil Khatri authored
Add support of gfx11 ipdump print so devcoredump could trigger it to dump the captured registers in devcoredump. Reviewed-by:
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Sunil Khatri authored
Add general registers of gfx11 in ipdump for devcoredump support. Reviewed-by:
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Sunil Khatri authored
IB1 registers: regCP_IB1_CMD_BUFSZ regCP_IB1_BASE_LO regCP_IB1_BASE_HI regCP_IB1_BUFSZ regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR Above registers are part of the asic but not of the offset file for gc_11_0_0_offset.h and hence adding them. Reviewed-by:
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Sunil Khatri authored
Adding more device information: a. PCI info b. VRAM and GTT info c. GDC config Also correct the print layout and section information for in devcoredump. Reviewed-by:
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Sunil Khatri authored
add prints before and after ip state is dumped. It avoids user to think of system being stuck/hung as dump could take some time after a gpu hang. Reviewed-by:
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Sunil Khatri authored
Add gfx queue register for all instances in devcoredump for gfx10. Reviewed-by:
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Sunil Khatri authored
Add support to dump registers of all instances of cp queue registers of gfx10 to devcoredump. Reviewed-by:
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Sunil Khatri authored
Rename the memory pointer from ip_dump to ip_dump_core to make it specific to core registers and rest other registers to be dumped in their respective memories. Reviewed-by:
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Lijo Lazar authored
KFD uses crc16 for gpu_id generation. Fixes: 3ed181b8 ("drm/amdkfd: Ensure gpu_id is unique") Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202405211405.TidTWIBX-lkp@intel.com/Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Kenneth Feng authored
this is a workaround to pass jpeg unit test on vcn 5.0 now. will be removed later. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Sonny Jiang <sonny.jiang@amd.com> Signed-off-by:
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Victor Zhao authored
the inst passed to amdgpu_virt_rlcg_reg_rw should be physical instance. Fix the miss matched code. Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Reviewed-by:
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Jane Jian authored
v1 - driver MMIO read the register to check whether write is required - if write is required, sriov full time to use rlcg, otherwise use KIQ v2 - include gfx v11 sriov runtime case Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Acked-by:
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Srinivasan Shanmugam authored
This commit modifies the construct_phy function to handle the case where `bios->integrated_info` is NULL and to address a compiler warning about a large stack allocation. Upon examination, it was found that the local `integrated_info` structure was just used to copy values which is large and was being declared directly on the stack which could potentially lead to performance issues. This commit changes the code to use `bios->integrated_info` directly, which avoids the need for a large stack allocation. The function now checks if `bios->integrated_info` is NULL before entering a for loop that uses it. If `bios->integrated_info` is NULL, the function skips the for loop and continues executing the rest of the code. This ensures that the function behaves correctly when `bios->integrated_info` is NULL and improves compatibility with dGPUs. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c: In function ‘construct_phy’: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_factory.c:743:1: warning: the frame size of 1056 bytes is larger than 1024 bytes [-Wframe-larger-than=] Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Jerry Zuo <jerry.zuo@amd.com> Cc: Qingqing Zhuo <qingqing.zhuo@amd.com> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Alvin Lee <alvin.lee2@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
hbm filed takes bit 13 and bit 14 in boot status. Signed-off-by:
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Frank Min authored
device_cntl2 is accessible from pci config space, so program it through pci cfg space instead of mmio. Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
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Li Ma authored
[Why] The vram width value is 0. Because the integratedsysteminfo table in VBIOS has updated to 2.3. [How] Driver needs a new intergrated info v2.3 table too. Then the vram width value will be correct. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
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Srinivasan Shanmugam authored
This commit fixes a format truncation issue arosed by the snprintf function potentially writing more characters into the ring->name buffer than it can hold, in the amdgpu_gfx_kiq_init_ring function The issue occurred because the '%d' format specifier could write between 1 and 10 bytes into a region of size between 0 and 8, depending on the values of xcc_id, ring->me, ring->pipe, and ring->queue. The snprintf function could output between 12 and 41 bytes into a destination of size 16, leading to potential truncation. To resolve this, the snprintf line was modified to use the '%hhu' format specifier for xcc_id, ring->me, ring->pipe, and ring->queue. The '%hhu' specifier is used for unsigned char variables and ensures that these values are printed as unsigned decimal integers. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c: In function ‘amdgpu_gfx_kiq_init_ring’: drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:61: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size between 0 and 8 [-Wformat-truncation=] 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | ^~ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:50: note: directive argument in the range [0, 2147483647] 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:332:9: note: ‘snprintf’ output between 12 and 41 bytes into a destination of size 16 332 | snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 333 | xcc_id, ring->me, ring->pipe, ring->queue); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 345a36c4 ("drm/amdgpu: prefer snprintf over sprintf") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: -
Jesse Zhang authored
Since the type of pg_flags is u32, adev->pg_flags >> 16 >> 16 is 0 regardless of the values of its operands. So removing the operations upper_32_bits and lower_32_bits. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
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Jack Xiao authored
Port mes11 hw_fini to mes12, fix for mode1 reset. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Jesse Zhang authored
Since the type of data_size is uint32_t, adev->umsch_mm.data_size - 1 >> 16 >> 16 is 0 regardless of the values of its operands So removing the operations upper_32_bits and lower_32_bits. Signed-off-by:
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Jesse Zhang authored
When user space sets an invalid ta type, the pointer context will be empty. So it need to check the pointer context before using it Signed-off-by:
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Jesse Zhang authored
Enum asic_type always greater than or equal CHIP_TAHITI. Signed-off-by:
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