- 06 Dec, 2022 40 commits
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Brian Masney authored
Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary in order to get PCIe working on the QDrive3. This patch also increases the width of the ranges property for the PCIe switch that's found on this platform. Note that this change requires the latest trustzone (TZ) firmware that's available from Qualcomm as of November 2022. If this is used against a board with the older firmware, then the board will go into ramdump mode when PCIe is probed on startup. The ranges property is overridden in this sa8540p-ride.dts file since this is what's used to describe the QDrive3 variant with dual SoCs. There's another variant of this board that only has a single SoC where this change is not applicable, and hence why this specific change was not done in sa8540p.dtsi. These changes were derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by:
Brian Masney <bmasney@redhat.com> Tested-by:
Andrew Halaney <ahalaney@redhat.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221202120918.2252647-1-bmasney@redhat.com
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Adam Skladowski authored
Add fallback to generic qcom mmu-500 implementation. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
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Adam Skladowski authored
Add WCN node to allow using wifi module. Signed-off-by:
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Adam Skladowski authored
Add I2C/SPI nodes for SM6115. Signed-off-by:
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Adam Skladowski authored
Add GPI DMA node which will be wired to i2c/spi/uart. Signed-off-by:
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Adam Skladowski authored
Add mdss and dpu node to enable display support on SM6115. Signed-off-by:
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Adam Skladowski authored
Add display clock controller to allow controlling display related clocks. Signed-off-by:
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Adam Skladowski authored
Add rpm stats node. Signed-off-by:
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Adam Skladowski authored
Add a node for the PRNG to enable hw-accelerated pseudo-random number generation. Signed-off-by:
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Adam Skladowski authored
Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by:
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Adam Skladowski authored
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by:
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Lin, Meng-Bo authored
WT88047 uses OCP 8110 Flash LED driver. Add it to the device tree. Signed-off-by:
Lin, Meng-Bo <linmengbo0689@protonmail.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and DT schema expects certain pattern: qcom/msm8998-oneplus-cheeseburger.dtb: leds: 'button-backlight' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' qcom/sc7180-trogdor-coachz-r1.dtb: pwmleds: 'keyboard-backlight' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' Signed-off-by:
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Parikshit Pareek authored
Introduce the Qualcomm SA8540P ride automotive platform, also known as Qdrive-3 development board. This initial contribution supports SMP, CPUFreq, cluster idle, UFS, RPMh regulators, debug UART, PMICs, remoteprocs and USB. The SA8540P ride contains four PM8450 PMICs. A separate DTSI file has been created for PMIC, so that it can be used for future SA8540P based boards. Signed-off-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Tested-by:
Eric Chanudet <echanude@redhat.com> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Tested-by:
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX223&224 DTSIs to better document the hardware. Diff between 223 and 224: < gpio-line-names = "NC", /* GPIO_0 */ < "NC", < "NC", < "NC", > gpio-line-names = "TELE_SPI_MISO", /* GPIO_0 */ > "TELE_SPI_MOSI", > "TELE_SPI_CLK", > "TELE_SPI_CS_N", < "PM8010_2_RESET_N", > "NC", < "NC", > "UWIDEC_PWR_EN", < "TOF_RST_N", > "NC" < "QLINK1_REQ", < "QLINK1_EN", /* GPIO_160 */ < "QLINK1_WMSS_RESET_N", > "NC", > "NC", /* GPIO_160 */ > "NC", The tele lens setup is different on 1 IV and 5 IV and power wiring is different for some lenses, so it makes sense. As for QLINK, no idea. Signed-off-by:
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Konrad Dybcio authored
This is a device property, not a bus host one. Signed-off-by:
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Manivannan Sadhasivam authored
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
The Vision Mezzanine for the RB5 ships with an imx577 and ov9282 populated. Other sensors and components may be added or stacked with additional mezzanines. Enable the IMX577 on the vision mezzanine. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -v -d /dev/media0 -V '"imx577 '22-001a'":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy2":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
Define the set of possible ports, one for each CSI PHY along with the port address and size cells @ the SoC dtsi level. Suggested-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Suggested-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by:
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Bryan O'Donoghue authored
Move the dts data for the rb3 navigation mezzanine into its own dts file. Suggested-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Bryan O'Donoghue authored
Use preferred "ok" not "okay". Use preferred status "disabled" instead of "disable". There's no functional change here so no Fixes has been applied. Reported-by:
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Bryan O'Donoghue authored
The reg for the port is specified in the dtsi. Remove from the db845c dts. Reviewed-by:
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Bryan O'Donoghue authored
sdm845.dtsi camss already defines the address-cells and size-cells for camss, no need to replicate in sdm845-db845c.dts. Reported-by:
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Bryan O'Donoghue authored
The number of available ports is SoC specific so we should define it in the SoC dtsi. For the case of the sdm845 that is 4 CSI PHYs => four ports. Reviewed-by:
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Konrad Dybcio authored
Adjust regulators, add required pin setup and finally enable SDHCI2 to get the SD Card slot going on Sagami Xperias. Signed-off-by:
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Sagami-common / PDX215 DTSIs to better document the hardware. Diff between 215 and common: < "NC", < "NC", > "WLC_I2C_SDA", > "WLC_I2C_SCL", < "NC", > "WLC_INT_N", > "CAM_MCLK4", < "NC", < "NC", > "TOF_RST_N", < "NC", < "NC", < "NC", > "QLINK1_REQ", > "QLINK1_EN", > "QLINK1_WMSS_RESET_N", It's pretty logical as 1 III has WLC (WireLess Charging), and an additional 3D iToF sensor. As for QLINK, no idea. Signed-off-by:
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Konrad Dybcio authored
Add and configure the SDHCI host responsible for (mostly) SD Card and its corresponding pins' sleep states. The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be broken). Signed-off-by:
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Johan Hovold authored
When recently adding the missing 'regulator-allowed-modes' properties it appears that the binding example with its four-spaces indentation (corresponding to a single tab, which is still to little) was copied verbatim. Drop the unnecessary first line break after 'regulator-allowed-modes' properties and indent the single remaining continuation line properly. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Remove unused and redundant sleep pin control entries as they are not referenced anywhere in sc7280 based platform's device tree variants. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Reported-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Konrad Dybcio authored
PMK8350 is the first PMIC to require both HLOS and PBS registers for PON to function properly (at least in theory, sm8350 sees no change). The support for it on the driver side has been added long ago, but it has never been wired up. Do so. Signed-off-by:
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Konrad Dybcio authored
Use the defines from qcom-rpmpd.h instead of bare numbers for readability. Signed-off-by:
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Konrad Dybcio authored
Use the defines from qcom-rpmpd.h instead of bare numbers for readability. Signed-off-by:
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Konrad Dybcio authored
Enable the newly added remote processors and assign them a firmware path. Signed-off-by:
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Konrad Dybcio authored
Add ADSP & CDSP remote processors. Signed-off-by:
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Konrad Dybcio authored
Add nodes for ADSP&CDSP SMP2P. Signed-off-by:
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Konrad Dybcio authored
Set SDHCI VMMC/VQMMC to <=2v96 and allow load setting by the SDHCI driver, as required by this use case. Configure the SD Card Detect pin, enable the SDHCI2 controller and assign it the aforementioned regulators. Signed-off-by:
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Konrad Dybcio authored
Add a pretty bog-standard-for-Xperias-for-the-past-3-years touchscreen setup. The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by:
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Konrad Dybcio authored
Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by:
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Konrad Dybcio authored
Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by:
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Konrad Dybcio authored
Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by:
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