- 25 May, 2023 16 commits
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the common DTSI to better document the hardware. The pin assignment for TLMM is identical on both devices. Great job! Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230315-topic-kumano_dts0-v2-2-0ca7fa521b86@linaro.org
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Konrad Dybcio authored
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Griffin and Bahamut device trees to better document the hardware. They are the same on both devices! Very nice! Signed-off-by:
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Dmitry Baryshkov authored
Unlike typical GIC interrupts, first cell for SPMI interrupts is the USID rather than GIC_SPI/GIC_PPI/GIC_LPI qualifier. Fix the resin interrupt to use USID value 0x0 rather than GIC_SPI define. Fixes: f86ae6f2 ("arm64: dts: qcom: sagit: add initial device tree for sagit") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Jagadeesh Kona authored
Add device node for video clock controller on Qualcomm SM8550 platform. Signed-off-by:
Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by:
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Taniya Das authored
Add device node for video clock controller on Qualcomm SM8450 platform. Signed-off-by:
Taniya Das <quic_tdas@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the SM8450 Video Clock Controller DeviceTree binding topic branch in order to get access to the clock constants defined by the binding.
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Taniya Das authored
Add device tree bindings for the video clock controller on Qualcomm SM8450 platform. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Robert Marko authored
Add node to support the QUP5 SPI controller inside of IPQ8074. Some devices use this bus in order to manage external switches. Signed-off-by:
Robert Marko <robimarko@gmail.com> Signed-off-by:
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Andrew Halaney authored
The mtl nodes aren't evaluated unless they're under the node with the compatible. Move them so they're now evaluated in case future patchsets modify them incorrectly. An example of this can be seen in the link. Link: https://lore.kernel.org/linux-arm-msm/20230414145844.wyg6pt623pzqwh5l@halaney-x13s/Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Reviewed-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
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Andrew Halaney authored
Using interrupts-extended already indicates what the interrupt-parent is, so drop the explicit interrupt-parent. The comment about this being the phy-intr is not helpful either, since this is the only interrupt in the phy node. Suggested-by:
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Andrew Halaney authored
The property logically makes sense in decimal, and is the standard used elsewhere. Suggested-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Andrew Halaney authored
As stated at the below link in another review, compatible is always the first property. Follow suit here to avoid copying incorrectly in the future. Link: https://lore.kernel.org/netdev/20230331215804.783439-1-ahalaney@redhat.com/T/#ma76b4116bbb9e49ee4bcf699e40935d80965b3f3Reviewed-by:
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Bhupesh Sharma authored
As noted by Konrad while reviewing [1], fix the EUD and DWC3 node syntax in sc7280 dtsi file. While at it also fix the errors reported by '$ make dtbs_check' for the EUD node: arch/arm64/boot/dts/qcom/sc7280-crd-r3.dtb: eud@88e0000: ports: 'oneOf' conditional failed, one must be fixed: 'port' is a required property '#address-cells' is a required property '#size-cells' is a required property From schema: Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml [1]. https://lore.kernel.org/linux-arm-msm/20221231131945.3286639-1-bhupesh.sharma@linaro.orgSigned-off-by:Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Neil Armstrong authored
Introduce sdam_2 node, which is to be used via nvmem for power on reasons during reboot. Add supported PoN reasons supported via sdam_2 node. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by:
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Neil Armstrong authored
Introduce sdam_2 node, which is to be used via nvmem for power on reasons during reboot. Add supported PoN reasons supported via sdam_2 node. Signed-off-by:
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Dmitry Baryshkov authored
Now as both lt9611 and drm/msm drivers were updated to handle the 4k modes over DSI, enable "bonded" DSI mode on DB845c. This way the board utilizes both DSI links and thus can support 4k on the HDMI output. Cc: Amit Pundir <amit.pundir@linaro.org> Signed-off-by:
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- 23 May, 2023 17 commits
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Bhupesh Sharma authored
Enable the aDSP and cDSP remoteproc nodes on Qualcomm QRB4210 RB2 board. Signed-off-by:
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Bhupesh Sharma authored
Card-Detect (CD) gpio for SDHC2 is an active GPIO line. Fix the same. This allows the uSD card to be properly detected on the board. Fixes: 8d58a8c0 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Reviewed-by:
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Bhupesh Sharma authored
Add the default and sleep pinctrl states for SDHC1 & 2 controllers on QRB4210 RB2 board. Reviewed-by:
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Konrad Dybcio authored
Enable the Microchip mcp2518fd hosted on the SPI5 bus. Signed-off-by:
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Konrad Dybcio authored
The MMC core calls regulator_set_load on VQMMC, enable loadsetting to make it effective. Fixes: 8d58a8c0 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by:
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Konrad Dybcio authored
Add the three LEDs (blue/yellow/green) connected to TLMM GPIOs. Signed-off-by:
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Konrad Dybcio authored
The RB2 has a HDMI output via an LT9611UXC bridge. Set it up. Signed-off-by:
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Konrad Dybcio authored
The board hosts a whole lot of fixed regulators. Describe them. Signed-off-by:
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Krzysztof Kozlowski authored
Add missing parts of USB stack to enable USB OTG mode. The QRD8550 comes with one USB Type-C port. Signed-off-by:
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Krzysztof Kozlowski authored
Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, thus skip pcie_1_phy_aux_clk input clock to GCC. Signed-off-by:
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Neil Armstrong authored
With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the Type-C connector, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Signed-off-by:
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Neil Armstrong authored
With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the Type-C connector, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Reviewed-by:
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Neil Armstrong authored
Add the USB3+DP Combo QMP PHY port subnodes in the SM8450 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by:
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Neil Armstrong authored
Add the USB3+DP Combo QMP PHY port subnodes in the SM8350 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by:
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Bjorn Andersson authored
The CRD has Micro SD slot, introduce the necessary DeviceTree nodes for enabling this. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
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Bjorn Andersson authored
Following the CRD, connect the two QMP phys inbetween the USB Type-C connectors and the DisplayPort controller, to handle orientation switching. Tested-by:
Abel Vesa <abel.vesa@linaro.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Bjorn Andersson authored
With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the two USB Type-C connectors, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Tested-by:
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- 18 May, 2023 7 commits
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Devi Priya authored
Drop unused bias_pll_ubi_nc_clk input to the clock controller. Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
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Devi Priya authored
Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR registers lie in the second 4kB region. Also, add target CPU encoding. Fixes: 97cb36ff ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support") Signed-off-by:
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André Apitzsch authored
l8910 uses OCP8110 flash LED driver. Add it to the device tree. Tested-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
André Apitzsch <git@apitzsch.eu> Signed-off-by:
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Konrad Dybcio authored
We need more granularity for things like the GPU. Add the missing levels. This unfortunately requires some re-indexing, resulting in an ugly diff. Rename the nodes to prevent that in the future. Signed-off-by:
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Konrad Dybcio authored
After adding the missing levels with a nice, easy-to-read diff, reformat the defines to make them nice to look at.. Acked-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Konrad Dybcio authored
There are a lot of RPMh levels that we haven't included yet.. some sadly turned out to be necessary, add them! Acked-by:
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Bartosz Golaszewski authored
The UFS controller is cache coherent, so mark it as such in the dtsi. Fixes: be543efe ("arm64: dts: qcom: sa8775p: add UFS nodes") Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Suggested-by:
Manivannan Sadhasivam <mani@kernel.org> Reviewed-by:
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