- 12 Feb, 2014 39 commits
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Daniel Vetter authored
Just a bit of polish which I hope will help me with massaging some internal patches to use Imre's reworked pipestat handling: - Don't check for underrun reporting or enable pipestat interrupts twice. - Frob the comments a bit. - Do the iir PIPE_EVENT to pipe mapping explicitly with a switch. We only have one place which does this, so better to make it explicit. v2: Ville noticed that I've broken the logic a bit with trying to avoid checking whether we're interested in a given pipe twice. push the PIPESTAT read down after we've computed the mask of interesting bits first to avoid that duplication properly. v3: Squash in fixups from Imre on irc. Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
We want to reuse this in the fbdev initial config code independently from any fastboot hacks. So allow a bit more flexibility. v2: Forgot to git add ... v3: make non-static (Jesse) Signed-off-by: -
Jesse Barnes authored
We want to do this early on before we try to fetch the plane config, which depends on some of the pipe config state. Note that the important part is that we do this before we initialize gem, since otherwise we can't properly pre-reserve the stolen memory for framebuffers inherited from the bios. v2: split back out from get_plane_config change (Daniel) update for recent locking & reset changes (Jesse) Signed-off-by:Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Explain a bit more why we need to move this.] Signed-off-by:
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Imre Deak authored
So far during driver unload we called drm_framebuffer_cleanup() for the fbdev fb, which only removes the fb from the drm fb list regardless of its reference count, but leaves the fb bound on an active crtc. Since the fb's backing storage was freed this could mean we scan some random memory content out afterwards. It's not a big issue since the fb is allocated from stolen memory and afaik there is no other user for that than i915. It's still cleaner to properly unbind the fb and disable the crtc, which is what drm_framebuffer_remove() does. Note that after commit 88891eb1e9eca0ba619518bed31580f91e9cf84d Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Mon Feb 10 18:00:38 2014 +0100 we call drm_framebuffer_cleanup() only after dropping the last reference on the fb, but that won't happen since we don't unbind the fb. This results in a drm core warn about a leaked fb. Signed-off-by:
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Ben Widawsky authored
Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
Deepak S <deepak.s@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by:
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Ben Widawsky authored
Everything can be overridden by module parameters, so don't confuse the users that are using them. We have RC6 turned on for all platforms which support it, but Ironlake, so the need to explain the situation is no longer pressing. Signed-off-by:
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Ben Widawsky authored
It wasn't ever used by the caller anyway with the exception of what we show in sysfs. Signed-off-by:
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Ben Widawsky authored
At one time, we though all future platforms would have the deeper RC6 states. As it turned out, they killed it after Ivybridge, and began using other means to achieve the power savings (the stuff we need to get to PC7+). The enable function was left in a weird state of odd corner cases as a result. Since the future is now, and we also have some insight into what's currently the future, we have an opportunity to simplify, and future proof the function. NOTE: VLV will be addressed in a subsequent patch. This patch was trying not to change functionality. NOTE2: All callers sanitize the return value anyway, so this patch is simply to have the code make a bit more sense. Signed-off-by:
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Paulo Zanoni authored
... and QUIRK_PIPEA_FORCE is not present. I initially thought that case was impossible and just added a WARN on it, but then I was told this case is possible due to QUIRK_PIPEA_FORCE. So let's add a WARN that serves two purposes: - tell us in case we have done something wrong; - document the only case where we expect this. Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Paulo Zanoni authored
Add a nice comment explaining why we shouldn't wait for a vblank on all cases, wait based on the HW gen, and add a comment saying we should probably skip that wait on some of the previous HW gens. Signed-off-by:
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Paulo Zanoni authored
Now that we pass struct intel_crtc as an argument, we can check for DSI inside the function, removing one more of those confusing boolean arguments. Signed-off-by:
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Paulo Zanoni authored
Now that we pass struct intel_crtc as an argument, there's no need for it. Signed-off-by:
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Paulo Zanoni authored
We want to remove those 3 boolean arguments. This is the first step. The "pipe" passed as the argument is always intel_crtc->pipe. Also adjust the function documentation. Signed-off-by:
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Paulo Zanoni authored
When I forked haswell_crtc_enable I copied all the code from ironlake_crtc_enable. The last piece of the function contains a big comment with a call to intel_wait_for_vblank. After this fork, we rearranged the Haswell code so that it enables the planes as the very last step of the modeset sequence, so we're sure that we call intel_enable_primary_plane after the pipe is really running, so the vblank waiting functions work as expected. I really believe this is what fixes the problem described by the big comment, so let's give it a try and get rid of that intel_wait_for_vblank, saving around 16ms per modeset (and init/resume). We can always revert if needed :) Signed-off-by:
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Paulo Zanoni authored
Because on Haswell, the pipe is never running at this point, so we hit the 50ms timeout waiting for nothing. We already have two other places where we wait for vblanks on haswell_crtc_enable, so we're safe. This gets us rid of one instance of "vblank wait timed out" for each mode set, which means driver init and resume are also 50ms faster. Signed-off-by:
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Paulo Zanoni authored
Depending on the HW gen and the connector type, the pipe won't start running right after we call intel_enable_pipe, so that intel_wait_for_vblank call we currently have will just sit there for the full 50ms timeout. So this patch adds an argument that will allow us to avoid the vblank wait in case we want. Currently all the callers still request for the vblank wait, so the behavior should still be the same. We also added a POSTING_READ on the register: previously intel_wait_for_vblank was acting as a POSTING_READ, but now if wait_for_vblank is false we'll stkip it, so we need an explicit POSTING_READ. Signed-off-by:
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Vandana Kannan authored
Instead of modifying intel_panel in lvds_init_connector/dsi_init/ edp_init_connector, making changes to move intel_panel->downclock_mode initialization to intel_panel_init() v2: Jani's review comments incorporated Removed downclock_mode local variable in dsi_init and edp_init_connector Signed-off-by:
Vandana Kannan <vandana.kannan@intel.com> Signed-off-by:
Pradeep Bhat <pradeep.bhat@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Jesse Barnes authored
Can be expanded up on to include all sorts of things (HDMI infoframe data, more DP status, etc). Should be useful for bug reports to get a baseline on the display config and info. v2: use seq_putc (Rodrigo) describe mode field names (Rodrigo) Reviewed-by: -
Jesse Barnes authored
Just like we have for connector type etc. v2: drop static array (Chris) v3: add kdoc (Daniel) Signed-off-by:
Dave Airlie <airlied@gmail.com> Signed-off-by:
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Jesse Barnes authored
For use by get_plane_config. v2: cleanup tile_height bits (Chris) Signed-off-by:
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Daniel Vetter authored
In Jesse's patch to switch the fbdev framebuffer from an embedded struct to a pointer the kfree in case of an error was missed. Fix this up by using our own internal fb allocation helper directly instead of reinventing that wheel. We need a to_intel_framebuffer cast unfortunately since all the other callers of _create still look better whith using a drm_framebuffer as return pointer. v2: Add an unlocked __intel_framebuffer_create function since our dev->struct_mutex locking is too much a mess. With ppgtt we even need it to take a look at the global gtt offset of pinned objects, since the vma list might chance from underneath us. At least with the current global gtt lookup functions. Reported by Mika. Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
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Daniel Vetter authored
Now that it's a normally kmalloce buffer we can use the usual cleanup paths. The upside here is that if we get the refcounting wrong will be able to catch it, since the drm core will complain about leftover framebuffers and kref about underflows. v2: Kill intel_framebuffer_fini - no longer needed now that we refcount all fbs properly and only confusing. v3: We actually still need to call unregister_private to remove the fb from the idr and drop the idr reference - the final unref doesn't do that. So much for remembering my own fb liftime rules. Reported by Imre Deak. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v2) Signed-off-by: -
Damien Lespiau authored
If we can't actually determine at run-time we have a fused-off display, provide at least an option to disable it. v2: Move the i915.disable_display test in a separate check (Daniel Vetter) Signed-off-by: -
Damien Lespiau authored
FUSE_STRAP has a bit to inform us that the display has been fused off. Use it to setup the definitive number of pipes at run-time. v2: actually tweak num_pipes, not num_planes v3: also tests SFUSE_STRAP bit 7 v4: rebase on top of drm-nightly use DRM_INFO() for the message telling display is fused off try to read the FUSE_LOCK bit to determine if PCH display is disabled v5: Don't read SFUSE_STRAP (register on the PCH) if num_pipes is already 0 from the initial device info struct (to prevent hangs) (Daniel Vetter) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (for v3) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (for v3) Signed-off-by: -
Chris Wilson authored
Arjan van de Ven reported that on his test machine that he was seeing stalls of greater than 1 frame greatly impacting the user experience. He tracked this down to being the locked flush during a pagefault as being the culprit hogging the struct_mutex and so blocking any other user from proceeding. Stalling on a pagefault is bad behaviour on userspace's part, for one it means that they are ignoring the coherency rules on pointer access through the GTT, but fortunately we can apply the same trick as the set-to-domain ioctl to do a lightweight, nonblocking flush of outstanding rendering first. "Prior to the patch it looks like this (this one testrun does not show the 20ms+ I've seen occasionally) 4.99 ms 2.36 ms 31360 __wait_seqno i915_wait_seqno i915_gem_object_wait_rendering i915_gem_object_set_to_gtt_domain i915_gem_fault __do_fault handle_ +pte_fault handle_mm_fault __do_page_fault do_page_fault page_fault 4.99 ms 2.75 ms 107751 __wait_seqno i915_gem_wait_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 4.99 ms 1.63 ms 1666 i915_mutex_lock_interruptible i915_gem_fault __do_fault handle_pte_fault handle_mm_fault __do_page_fault do_page_fault page_fa +ult 4.93 ms 2.45 ms 980 i915_mutex_lock_interruptible intel_crtc_page_flip drm_mode_page_flip_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_ +sysret 4.89 ms 2.20 ms 3283 i915_mutex_lock_interruptible i915_gem_wait_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 4.34 ms 1.66 ms 1715 i915_mutex_lock_interruptible i915_gem_pwrite_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 3.73 ms 3.73 ms 49 i915_mutex_lock_interruptible i915_gem_set_domain_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 3.17 ms 0.33 ms 931 i915_mutex_lock_interruptible i915_gem_madvise_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 2.97 ms 0.43 ms 1029 i915_mutex_lock_interruptible i915_gem_busy_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 2.55 ms 0.51 ms 735 i915_gem_get_tiling drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret After the patch it looks like this: 4.99 ms 2.14 ms 22212 __wait_seqno i915_gem_wait_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 4.86 ms 0.99 ms 14170 __wait_seqno i915_gem_object_wait_rendering__nonblocking i915_gem_fault __do_fault handle_pte_fault handle_mm_fault __do_page_ +fault do_page_fault page_fault 3.59 ms 1.31 ms 325 i915_gem_get_tiling drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 3.37 ms 3.37 ms 65 i915_mutex_lock_interruptible i915_gem_wait_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 2.58 ms 2.58 ms 65 i915_mutex_lock_interruptible i915_gem_do_execbuffer.isra.23 i915_gem_execbuffer2 drm_ioctl i915_compat_ioctl compat_sys_ioctl +ia32_sysret 2.19 ms 2.19 ms 65 i915_mutex_lock_interruptible intel_crtc_page_flip drm_mode_page_flip_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_ +sysret 2.18 ms 2.18 ms 65 i915_mutex_lock_interruptible i915_gem_busy_ioctl drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret 1.66 ms 1.66 ms 65 i915_gem_set_tiling drm_ioctl i915_compat_ioctl compat_sys_ioctl ia32_sysret It may not look like it, but this is quite a large difference, and I've been unable to reproduce > 5 msec delays at all, while before they do happen (just not in the trace above)." gem_gtt_hog on an old Pineview (GMA3150), before: 4969.119ms after: 4122.749ms Reported-by:
Arjan van de Ven <arjan.van.de.ven@intel.com> Testcase: igt/gem_gtt_hog Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Atm we call the handlers for pending pipestat interrupt events even if they aren't explicitly enabled by i915_enable_pipestat(). This isn't an issue for events other than the vblank start event, since those are always enabled anyways. Otoh, we enable the vblank start event on-demand, so we'll end up calling the vblank handler at times when they are disabled. I haven't checked if this causes any real problem, but for consistency and to remove some overhead we should still fix this by clearing / handling only the enabled interrupt events. Also this is a dependency for the upcoming VLV power domain patchset where we need to disable all the pipestat interrupts whenever the display power well is off. v2: - inline the status->enable mask mapping (Ville) - don't check for invalid PSR bit on platforms other than VLV (Ville) Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Frob conflict due to different merge order.] Signed-off-by:
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Imre Deak authored
At least on VLV we can't get at the pipestat status bits by simply right shifting the corresponding enable bits. The mapping between enable and status bits for the sprite0,1 flip done and the PSR events don't follow this rule, so we need to map them separately. The PSR enable for pipe A is DPFLIPSTAT[22], but I haven't added support for this, since there is no user of it atm. Until support is added WARN if someone tries to enable PSR interrupts, or tries to enable the same (1 << 6) bit on pipe B, which MBZ. v2: - inline the status->enable mask mapping (Ville) - fix bogus use of status bits in enable mask (Ville) Signed-off-by:
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Imre Deak authored
There isn't any PSR interrupt enable bit for pipe A, so we couldn't enable it through the current API. Passing the corresponding status bits solves this and also makes the mapping between enable and status bits simpler on VLV (addressed in an upcoming patch). Except of checking for invalid status bit arguments, no functional change. v2: split out the low level parts of i915_enable_pipestat accepting separate enabled and status masks, to make the non-standard mapping between those masks stand out more (added in the next patch) (Jesse,Daniel) Signed-off-by: -
Chris Wilson authored
Touching the VGA registers risks a hard machine hang, at least on this ivb machine after removing a conflicting efifb. This is more than likely related to the discovery that VGA IO decode on the more recent PCH platforms is terminally broken. Signed-off-by:
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Chris Wilson authored
This has very little effect other than log the errors in case of failure, and we then hope for the best. Signed-off-by:
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Jesse Barnes authored
Allocate this struct instead, so we can re-use another allocated elsewhere if needed. Signed-off-by:
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Chris Wilson authored
When we detect that the user passed along an invalid handle or object, we emit a warning as an aide for debugging. Since these are indeed only for debugging user triggerable errors (and the errors are reported back to userspace by the errno), the messages should only be at the debug level and not claiming that there is a catastrophic error in the driver/hardware. References: https://bugs.freedesktop.org/show_bug.cgi?id=74704Signed-off-by:
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Damien Lespiau authored
Signed-off-by:
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Damien Lespiau authored
Reviewed-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
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Damien Lespiau authored
We had 2 set of defines for the same register, so make it one. Reviewed-by:
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Damien Lespiau authored
And rename it to num_sprites as this value doesn't count the primary plane. This limit lives with num_pipes really, and now that dev_priv->info is writable we can put it there instead. While at it, introduce a intel_device_info_runtime_init() where we'll be able to gather the device info fields at run-time. v2: rename num_plane to num_sprites (Ville Syrjälä) v3: rebase on top of latest drm-nightly Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (for v2) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (for v2) Signed-off-by:
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Damien Lespiau authored
Turns out it'd be nice to change some device information at run-time or simply have some code to fill in the info struct instead of having to declare the values in 30+ structures. What prompted this change is handling fused out display/pipe and tweaking num_pipes at run-time, but I'm quite sure we'll find other flags/limits to stick into dev_priv->info. Most of the changes were done with a sed: sed -i -e 's/dev_priv->info->/dev_priv->info./g' drivers/gpu/drm/i915/*[ch] with a few tweaks to make it all work: - Change the field definition in struct drm_i915_private - adjust i915_dump_device_info() - adjust i915_driver_load() - adjust the INTEL_INFO() macro v2: cast the info pointer returned by INTEL_INFO() to be const to catch uses that would modify the structure post-initialization. (Ville Syrjälä) v3: Redo the patch onto latest drm-nightly, Keep the info field const to catch post initialization writes instead of the v2 solution, Use a direct structure copy for the initial info initialization to use the compiler type safety (Ville Syrjälä) Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> (for v2) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (for v2) Signed-off-by: -
Damien Lespiau authored
If we make sure that all the dev_priv->info usages are wrapped by INTEL_INFO(), we can easily modify the ->info field to be structure and not a pointer while keeping the const protection in the INTEL_INFO() macro. v2: Rebased onto latest drm-nightly Suggested-by:
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Ville Syrjälä authored
According to Bspec we need to disable SF pipelined attribute fetch whenever SF outputs exceed 16 and normal clip mode is used. A quick glance at Mesa suggests that these conditions could happen. So let's just always set the magic bit. Signed-off-by:
Kenneth Graunke <kenneth@whitecape.org> Signed-off-by:
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- 07 Feb, 2014 1 commit
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Jeff McGee authored
sysfs changes to rps min and max delay were only triggering an update of the rps interrupt limits if the active delay required an update. This change ensures that interrupt limits are always updated. v2: correct compile issue missed on rebase v3: add igt testcases to signed-off-by section Testcase: igt/pm_rps/min-max-config-idle Testcase: igt/pm_rps/min-max-config-loaded Signed-off-by:
Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
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