* pci/host-qcom:
  PCI: qcom: Limit TLP size to 2K to work around hardware issue
  PCI: qcom: Fix spelling mistake: "asser" -> "assert"
  PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc
  PCI: qcom: Add support for IPQ4019 PCIe controller

* pci/host-mediatek:
  dt-bindings: PCI: Add documentation for MediaTek PCIe
  PCI: mediatek: Add MediaTek PCIe host controller support

* pci/host-kirin:
  PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driver

Add documentation for PCIe host driver available in MT7623 series SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>

* pci/host-imx6:
  PCI: imx6: Add regulator support

* pci/host-hv:
  PCI: hv: Use vPCI protocol version 1.2
  PCI: hv: Add vPCI version protocol negotiation
  PCI: hv: Temporary own CPU-number-to-vCPU-number infra
  PCI: hv: Use page allocation for hbus structure
  PCI: hv: Fix comment formatting and use proper integer fields

* pci/host-faraday:
  PCI: faraday: Add clock handling
  PCI: faraday: Add clock bindings

* pci/host-dra7xx:
  PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN
  PCI: dwc: dra7xx: Depend on appropriate SoC or compile test

* pci/host-designware:
  PCI: dwc: Constify dw_pcie_host_ops structures
  PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD

* pci/irq-fixups:
  arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq()
  PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions
  PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions
  PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions
  PCI: altera: Drop pci_fixup_irqs()
  PCI: versatile: Drop pci_fixup_irqs()
  PCI: generic: Drop pci_fixup_irqs()
  PCI: faraday: Drop pci_fixup_irqs()
  PCI: designware: Drop pci_fixup_irqs()
  PCI: iproc: Drop pci_fixup_irqs()
  PCI: rcar: Drop pci_fixup_irqs()
  PCI: xilinx: Drop pci_fixup_irqs()
  PCI: tegra: Drop pci_fixup_irqs()
  ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers
  PCI: Add a call to pci_assign_irq() in pci_device_probe()
  OF/PCI: Update of_irq_parse_and_map_pci() comment
  PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it
  PCI: Add IRQ mapping function pointers to pci_host_bridge struct
  PCI: Build setup-irq.o on all arches
  PCI: Remove pci_scan_root_bus_msi()
  PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge()
  ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge()
  PCI: Make pci_register_host_bridge() PCI core internal
  PCI: Add pci_scan_root_bus_bridge() interface
  PCI: tegra: Fix host bridge memory leakage
  PCI: faraday: Fix host bridge memory leakage
  PCI: Add devm_pci_alloc_host_bridge() interface
  PCI: Add pci_free_host_bridge() interface
  PCI: Initialize bridge release function at bridge allocation
  PCI: faraday: Convert IRQ masking to raw PCI config accessors
  PCI: iproc: Convert link check to raw PCI config accessors
  PCI: xilinx-nwl: Remove nwl_pcie_enable_msi() unused bus parameter

* pci/virtualization:
  PCI: Remove __pci_dev_reset() and pci_dev_reset()
  PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done()
  PCI: Protect pci_error_handlers->reset_notify() usage with device_lock()
  PCI: Protect pci_driver->sriov_configure() usage with device_lock()
  PCI: Mark Intel XXV710 NIC INTx masking as broken
  PCI: Restore PRI and PASID state after Function-Level Reset
  PCI: Cache PRI and PASID bits in pci_dev

Implement the reset probing / reset chain directly in
__pci_probe_reset_function() and __pci_reset_function_locked()
respectively.

Link: http://lkml.kernel.org/r/20170601111039.8913-4-hch@lst.deSigned-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

The pci_error_handlers->reset_notify() method had a flag to indicate
whether to prepare for or clean up after a reset.  The prepare and done
cases have no shared functionality whatsoever, so split them into separate
methods.

[bhelgaas: changelog, update locking comments]
Link: http://lkml.kernel.org/r/20170601111039.8913-3-hch@lst.deSigned-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

* pci/switchtec:
  switchtec: Add device IDs for additional Switchtec products
  switchtec: Add "running" status flag to fw partition info ioctl

* pci/resource:
  PCI: Work around poweroff & suspend-to-RAM issue on Macbook Pro 11
  PCI: Do not disregard parent resources starting at 0x0

Conflicts:
arch/x86/pci/fixup.c

* pci/portdrv:
  PCI/portdrv: Allocate MSI/MSI-X vector for Downstream Port Containment
  PCI/portdrv: Support multiple interrupts for MSI as well as MSI-X

* pci/pm:
  PCI/PM: Avoid using device_may_wakeup() for runtime PM
  x86/PCI: Avoid AMD SB7xx EHCI USB wakeup defect
  PCI/PM: Restore the status of PCI devices across hibernation
  drm/radeon: make MacBook Pro d3_delay quirk more generic
  drm/amdgpu: remove unnecessary save/restore of pdev->d3_delay
  PCI/PM: Add needs_resume flag to avoid suspend complete optimization
  PCI: imx6: Fix config read timeout handling
  switchtec: Fix minor bug with partition ID register
  switchtec: Use new cdev_device_add() helper function
  PCI: endpoint: Make PCI_ENDPOINT depend on HAS_DMA

* pci/msi:
  PCI/MSI: Ignore affinity if pre/post vector count is more than min_vecs

* pci/misc:
  x86/PCI: Simplify Dell DMI B1 quirk
  PCI: Add domain number check to find_smbios_instance_string()
  x86/PCI: Fix whitespace in set_bios_x() printk
  PCI: Correct PCI_STD_RESOURCE_END usage
  efi/fb: Correct PCI_STD_RESOURCE_END usage
  MIPS: PCI: Remove unused busn_offset
  MIPS: Loongson: Remove unused PCI_BAR_COUNT definition

* pci/enumeration:
  PCI: Enable ECRC only if device supports it
  PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc
  PCI: Test INTx masking during enumeration, not at run-time

* pci/dpc:
  PCI/DPC: Fix control register setting
  PCI/DPC: Skip DPC event if device is not present

Limit TLP size to 2K to work around a hardware bug in the v0 version of
PCIe IP.  When using default TLP size of 4K, the internal buffer gets
corrupted due to this hardware bug.

This bug was originally noticed during ssh session between APQ8064-based
board and PC.  Network packets got corrupted randomly and terminated the ssh
session due to this bug.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Trivial fix to spelling mistake in dev_err message.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Previously the v0, v1, and v2 functions were not grouped together in a
consistent order.  Reorder them to make them consistent.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Add support for the IPQ4019 PCIe controller.  IPQ4019 supports Gen 1/2, one
lane, one PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.

The core init is the same as for the MSM8996, however the clocks and reset
lines differ.

[bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile
issues]
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Acked-by: Rob Herring <robh@kernel.org>		# binding

Add support for the MediaTek PCIe Gen2 controller which can be found on
MT7623 series SoCs.

[bhelgaas: fold in mtk_pcie_parse_and_add_res() bugfix from
http://lkml.kernel.org/r/1496644078-27122-1-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in MAINTAINERS update from
http://lkml.kernel.org/r/1497588789-28607-1-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in pci_scan_root_bus_bridge() update and leak fix from
http://lkml.kernel.org/r/1498555451-55073-2-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in powerup fixes from
http://lkml.kernel.org/r/1497866400-41844-2-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in poweroff when link down fixes from
http://lkml.kernel.org/r/1497866400-41844-3-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: fold in optional property fixes from
http://lkml.kernel.org/r/1497866400-41844-4-git-send-email-ryder.lee@mediatek.com]
[bhelgaas: set host->map_irq and host->swizzle_irq and drop
pci_fixup_irqs(), remove unnecessary "return", rename mtk_pcie_link_is_up()
to mtk_pcie_link_up() for consistency, add local struct device pointer]
[bhelgaas: fold in pci_add_flags() removal from
http://lkml.kernel.org/r/1499061300-55951-1-git-send-email-ryder.lee@mediatek.com]
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Hisilicon PCIe driver shares the common functions for PCIe dw-host.

The poweron functions are developed on hi3660 SoC, while other functions
are common for Kirin series SoCs.

Low power mode (L1 sub-state and Suspend/Resume), hotplug and MSI feature
are not supported currently.
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
[bhelgaas: fold in MAINTAINERS update from
http://lkml.kernel.org/r/20170704021516.96575-1-songxiaowei@hisilicon.com]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Cc: Guodong Xu <guodong.xu@linaro.org>

Some boards might require to control a regulator to power the PCIe port.

Add support for an optional regulator defined in Device Tree linked in the
PCIe controller under `vpcie-supply`.  If present, the regulator will be
disabled and then enabled as part of the PCIe host initialization process
and will be disabled when shutting down.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
[bhelgaas: use dev_err() instead of pr_err() in
imx6_pcie_assert_core_reset()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>

Update the Hyper-V vPCI driver to use the Server-2016 version of the vPCI
protocol, fixing MSI creation and retargeting issues.
Signed-off-by: Jork Loeser <jloeser@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>

Hyper-V vPCI offers different protocol versions.  Add the infra for
negotiating the one to use.
Signed-off-by: Jork Loeser <jloeser@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>

To ease parallel effort to centralize CPU-number-to-vCPU-number conversion,
temporarily stand up own version, file-local hv_tmp_cpu_nr_to_vp_nr().
Once the changes have merged, this work-around can be removed, and the
calls replaced with hv_cpu_number_to_vp_number().
Signed-off-by: Jork Loeser <jloeser@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>

The hv_pcibus_device structure contains an in-memory hypercall argument
that must not cross a page boundary.  Allocate the structure as a page to
ensure that.
Signed-off-by: Jork Loeser <jloeser@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>

Fix comment formatting and use proper integer fields.
Signed-off-by: Jork Loeser <jloeser@microsoft.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: K. Y. Srinivasan <kys@microsoft.com>
Acked-by: K. Y. Srinivasan <kys@microsoft.com>

Add some optional clock handling to the Faraday FTPCI100.  We just get and
prepare+enable the clocks right now, if they exist.  We can add more
elaborate clock handling later.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[bhelgaas: folded in "Make clocks compulsory" fix from
http://lkml.kernel.org/r/20170621085730.28804-1-linus.walleij@linaro.org
Also folded in the clock max/cur speed fixes from
http://lkml.kernel.org/r/20170621162651.25315-1-linus.walleij@linaro.org]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.  Add
bindings for these two clocks so we can assign them in the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>

Previously, we tried to clear interrupt requests by clearing bits in the
PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI and PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN
registers.  But per the TRM, these fields are RW1C, so we must *set* bits
to clear the interrupt bits.

Fixes: 47ff3de9 ("PCI: dra7xx: Add TI DRA7xx PCIe driver")
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

The PCI controller attached to a SoC isn't much use if the core SoC isn't
enabled, unless of course it's compile testing, so add appropriate
dependency.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

The dw_pcie_host_ops structures are never modified.  Constify these
structures such that these can be write-protected.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>

Similar as commit 8ff0ef99 ("PCI: host: Mark PCIe/PCI (MSI) IRQ cascade
handlers as IRQF_NO_THREAD"), we should mark PCIe/PCI (MSI) IRQ cascade
handlers in designware, qcom, and vmd as IRQF_NO_THREAD explicitly.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Keith Busch <keith.busch@intel.com>	# vmd
Acked-by: Jingoo Han <jingoohan1@gmail.com>	# pcie-designware-plat.c

With the introduction of struct pci_host_bridge.map_irq pointer it is
possible to assign IRQs for all devices originating from a PCI host bridge
at probe time; this is implemented through pci_assign_irq() that relies on
the struct pci_host_bridge.map_irq pointer to map IRQ for a given device.

The benefits this brings are twofold:

  - the IRQ for a device is assigned once at probe time
  - the IRQ assignment works also for hotplugged devices

With all DT based PCI host bridges converted to the struct
pci_host_bridge.{map/swizzle}_irq hooks mechanism the DT IRQ allocation in
ARM64 pcibios_alloc_irq() is now redundant and can be removed.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will.deacon@arm.com>