- 01 Jul, 2020 40 commits
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Nirmoy Das authored
If (smu)->ppt_funcs->intf is not initialized then smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32) and smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32) will not touch bottom32 and top32. Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] Regression was introduced where setting max bpc property has no effect on the atomic check and final commit. It has the same effect as max bpc being stuck at 8. [How] Correctly propagate max bpc with the new connector state. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Add debug flag for psr to use hw locking mgr state machine Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Wenjing Liu authored
[why] DP link layer CTS specs updated to change the test parameters in test 4.2.1.1. Before it requires source to delay 400us on aux no reply. With the specs updates Errata5, it requires source to delay 3.2ms (based on LTTPR aux timeout) This causes our test to fail after updating with the latest test equipment firmware. [how] the change is to allow LTTPR 3.2ms aux timeout delay by default. And set back to 400us if LTTPR feature is not enabled. We will set 3.2ms and always enable LTTPR non transparent mode if LTTPR feature is enabled and LTTPR is present. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Wenjing Liu authored
[why] Two issues: 1. Add read only operation support for query ddc data over aux. 2. Fix a bug where if read size is multiple of 16, mot of the last read transaction will not be set to 0. Signed-off-by:
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David Galiffi authored
[Why] If the front porch of the two timings differ, then there may not be enough time while both streams are in vertical blank to perform a memory clock change. This can hang the system. [How] Check the each streams timing.v_front_porch when determining if the two streams are synchronizable. Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Martin Leung authored
why: seamless boots requires split of init_hw into hw and pipes to work. This was implemented in dcn10_init_hw but did not apply yet to dcn30. how: Copy over dcn10_init_hw and adapt it to dcn30 using recent changes to dcn3. Behavior will be different in init sequence. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Peikang Zhang authored
[Why] We try to to change new_clocks->dppclk_khz to 100000 when new_clocks->dppclk_khz is 0 [How] Don't change new_clocks->dppclk_khz value when new_clocks->dppclk_khz is 0 Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Chris Park authored
[Why] 10K YCbCr420 does not need ODM 4:1, but it requires MPC 4 split indicated on the flags. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Derek Lai authored
[why] If a typeC to HDMI dongle supports YCbCr420 pass through and VSC colorimetry and pixel encoding formats in the Extended Receiver Capability, we shall allow VSC SDP to be used. [How] The Extended Receiver Capability field shall check the EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT bit in the TRAINING_AUX_RD_INTERVAL register. Removed DPCD rev checking for VSC SDP. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] DMCUB firmware version is now available from firmware metadata block. We should be passing this into dmub_srv so we can know when to apply firmware version specific functionality like using CW4 only instead of the REGION4. [How] We don't have the helpers for DM to actually extract out firmware metadata block themselves. We could add that and add helpers in DM to grab this, but not every creation sequence has firmware instruction before dmub_srv_create. Easiest way to handle this is to fill this in automatically per DM in the place we do have it - when calculating the region parameters. But only fill it in if DM already hasn't in case we need to override with a specific version. We aren't do anything firmware version specific in dmub_srv_create today that does require fw_version, so while it's a little unituitive to do it when calculating region parameters it works for now. Signed-off-by:
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Stylon Wang authored
[Why] Connector property output_bpc is available on DP/eDP only. New IGT tests would benifit if this property works on HDMI. [How] Enable this read-only property on all types of connectors. Signed-off-by:
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Chris Park authored
[Why] All YCbCr420 resolutions 5K and above have tiling and discoloration issues. The issue can be remedied by forcing ODM combine from 5K to 8K. 10K resolution requires ODM 4:1. The mechanism of what the real problem is, that is inherent in ODM combine programming, doesn't seem to be pointed at singular register programming (CLK, MPC, DCSURF, etc.), and needs more in-depth programming sequence review for these new use case scenarios. Until then, workaround to enable ODM combine is proposed. While it is not our policy, HW spreadsheet also recommends turning on ODM for these scenario to lower the voltage. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Brandon Syu authored
[Why] There is using pixelclk AVFS for dppclk, that would cause issue. [How] To use dispclk AVFS for both dispclk and dppclk. There would choose dppclk for request voltage when dispclk wouldn't be updated case. If dispclk need to be updated, then it'll choose the bigger one from dppclk and dispclk for request voltage. Signed-off-by:
Brandon Syu <Brandon.Syu@amd.com> Reviewed-by:
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Eric Yang authored
[Why] If optimized init is done in FW. DCN init be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Dale Zhao authored
[WHY] Check max_tmds_clk_mhz firstly will restrict pixel clock under HDMI 1.4, thus HDMI2.0 port can't correctly support 4K 60Hz. [HOW] Fine tune the logic to check max_forum_tmds_clk_mhz firstly. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
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Jake Wang authored
[Why & How] Need to check if local_sink is NULL before accessing. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why] DC global validation can fail when userspace requests to draw large plane without performing the clipping themselves. This is observed in the IGT kms_plane panning tests for 4K displays where they draw an 8K plane without any clipping while expecting only the top 4K to be drawn. [How] DRM already has helpers to take care of the clipping necessary and to mark whether a plane is visible or not, so make use of these helpers in DM before passing the plane to DC. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Anthony Koo authored
[Header Changes] - Update scratch information for boot status Signed-off-by:
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Camille Cho authored
[Why] dc_link_set_psr_allow_active() always returns true, even in the case that PSR is not supported. [How] Hook up the return value of dc_link_set_psr_allow_active(). Signed-off-by:
Camille Cho <Camille.Cho@amd.com> Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Side-by-side and Top-and-bottom stereo configurations fail DML mode validation due to Viewport exceeded. This is because we consider the planes as being pipe split in pipe population so we end up doubling the viewport width, eg. from 4k to 8k. [How] These pipes technically aren't hsplit, so add a check for determining whether is_hsplit should be set. Signed-off-by:
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Bhawanpreet Lakha authored
[Why] assr is content protection for eDP, in order to use it we need to call psp ta (dtm) [How] We have a enable_assr callback, hook into this and call the correct psp cmd id to enable assr. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Michael Strauss authored
[WHY] Currently DC doesn't check requested pixel clock against an EDID specified TMDS max clock if it exists, passing modes that should fail [HOW] Add max TMDS clk to edid caps and perform check during validation Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
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Yi-Ling Chen authored
[why] dc->hwss->edp_backlight_control is null, it would casue it only be off main-link of eDP. It is not worng behavior for eDP power sequence off. [how] Must use hwseq->funcs.edp_backlight_control finction pointer for edp backlight. Signed-off-by:
Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Reviewed-by:
Sung Lee <Sung.Lee@amd.com> Acked-by:
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Mikita Lipski authored
[why] The calculation of virtual channel payload would not take link settings in account. As we calculate VCPI slots needed both PBN for stream and also PBN per time slot. Before we would use generic PBN per time slot, which would not change with link settings causing wrong Payload allocation. [how] Provide PBN per time slot for each Virtual channel payload calculation. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
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Wyatt Wood authored
[Why] Hw lock manager adds the ability to lock pipe, cursor, and dig in fw. [How] Send hw lock command to fw to lock pipe, cursor, and dig. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Sonny Jiang authored
Enable asic Verde, Tahiti and Pitcairn UVD block. Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
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Sonny Jiang authored
Enable Oland UVD block. Signed-off-by:
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Sonny Jiang authored
Signed-off-by:
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Sonny Jiang authored
Implement SI uvd_ctx_rreg/wreg functions. Signed-off-by:
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Sonny Jiang authored
Implement SI UVD. The SI UVD firmware requires validation. v2: squash in missing brace fix (Colin Ian King) Signed-off-by:
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Sonny Jiang authored
Add SI UVD registers files. Signed-off-by:
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Sonny Jiang authored
Fix packet_type0 definition in sid. Signed-off-by:
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Sonny Jiang authored
For implement UVD on SI asic, add Oland, Pitcairn, Verde, Tahiti firmwares. Signed-off-by:
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Alex Deucher authored
drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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