- 19 Jan, 2023 7 commits
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Biao Huang authored
Add Ethernet controller node for mt8195. Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
Biao Huang <biao.huang@mediatek.com> Link: https://lore.kernel.org/r/20230105010712.10116-3-biao.huang@mediatek.comSigned-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Chen-Yu Tsai authored
The scp_adsp clock controller is under the SCP_ADSP power domain. This power domain is currently not supported nor defined. Mark the clock controller as broken for now, to avoid the system from trying to access it, and causing the CPU or bus to stall. Fixes: 5d2b897b ("arm64: dts: mediatek: Add mt8192 clock controllers") Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Tested-by:
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Alexandre Mergnat authored
- Change the node name from "mt6397" to "pmic" to be consistent with the generic names recommendation. Signed-off-by:
Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by:
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Alexandre Mergnat authored
- Change the node name from "mt6358" to "pmic", "mt6358rtc" to "rtc" and "mt6358keys" to "keys" to be consistent with the generic names recommendation. Signed-off-by:
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Allen-KH Cheng authored
Add DPI node for MT8186 SoC. Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by:
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Allen-KH Cheng authored
Add audio controller node for MT8186 SoC. Signed-off-by:
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Allen-KH Cheng authored
Add ADSP mailbox node for MT8186 SoC. Signed-off-by:
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- 13 Jan, 2023 4 commits
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Frank Wunderlich authored
Add support for Bananapi R3 SBC. - SD/eMMC support (switching first 4 bits of data-bus with sw6/D) - SPI-NAND/NOR support (switched CS by sw5/C) - all rj45 ports and both SFP working (eth1/lan4) - all USB-Ports + SIM-Slot tested - i2c and all uarts tested - wifi tested (with eeprom calibration data) The device can boot from all 4 storage options. Both, SPI and MMC, can be switched using hardware switches on the board, see https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_settingSigned-off-by:
Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.deSigned-off-by:
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Sam Shih authored
This patch adds PCIe support for MT7986. Signed-off-by:
Jieyy Yang <jieyy.yang@mediatek.com> Signed-off-by:
Sam Shih <sam.shih@mediatek.com> Signed-off-by:
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Sam Shih authored
This patch adds mmc support for MT7986. Signed-off-by:
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Sam Shih authored
This patch adds USB support for MT7986. Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.deSigned-off-by:
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- 09 Jan, 2023 28 commits
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Allen-KH Cheng authored
For crypto support, add a crypto clock of the inline crypto engine and expand the register size in the eMMC controller. Signed-off-by:
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AngeloGioacchino Del Regno authored
Configure the sound card on all MT8195 Cherry Tomato devices to enable audio support. Signed-off-by:
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AngeloGioacchino Del Regno authored
The entire Cherry family has two digital microphones, for which we use the generic dmic-codec, linked to the MT6359 PMIC. Moreover, it uses a Realtek RT1019p amplifier for the speakers and has either a Realtek RT5682i or RT5682s audio codec on I2C2: specifically, RT5682i is found on Tomato's rev 1 and rev 2 boards, while RT5682s is found in rev3 and rev4 boards. Signed-off-by:
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AngeloGioacchino Del Regno authored
This platform is able to use the Audio DSP embedded into the MT8195 SoC: in preparation for adding audio support for Cherry, add the ADSP related memory nodes and enable it. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for adding audio support, enable the AFE HW with the appropriate eTDM configuration and memory region. Signed-off-by:
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Krzysztof Kozlowski authored
The node names should be generic and DT schema expects certain pattern: mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dtb: pwmleds: 'keyboard-backlight' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221125144138.477198-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Nícolas F. R. A. Prado authored
Add aliases for the i2c and mmc nodes on the Asurada platform DT to ensure that we get stable ids for those devices on userspace. Reviewed-by:
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Nícolas F. R. A. Prado authored
Enable audio support for the Asurada platform. This consists of the machine sound card, the rt1015p codec for the speakers, the rt5682 codec for the headset, and the dmic codec for the internal microphone. Newer revisions of spherion and hayato use the rt5682s codec for the headset instead, so the codecs and card compatible are added through separate dtsi files to prepare for that. HDMI audio support is left out for now since the DisplayPort chip required isn't enabled yet. Tested-by:
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Nícolas F. R. A. Prado authored
The asurada platform has an ANX7625 bridge connecting the DSI's output to the internal eDP panel. Add and enable these devices in order to get a usable internal display. Reviewed-by:
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Nícolas F. R. A. Prado authored
Add the display backlight for the Asurada platform. It relies on the display PWM controller, so also enable and configure this component. Reviewed-by:
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Nícolas F. R. A. Prado authored
Add the regulators present on the Asurada platform that are used to power the internal and external displays. Reviewed-by:
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AngeloGioacchino Del Regno authored
This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically, four CPUs per cluster, with two CPU clusters. Each CPU has: - A 32KB I-cache, 2-way set associative; - A 32KB D-cache, 4-way set associative. Each cluster has a unified 1MB L2 cache, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by:
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AngeloGioacchino Del Regno authored
This SoC features two clusters composed of: - 4x Cortex A53: 32KB I-cache, 2-way set associative, 32KB D-cache, 4-way set associative, unified 1MB L2 cache, 16-way set associative; - 4x Cortex A73: 64KB I-cache and 64KB D-cache, 4-way set associative, unified 1MB L2 cache, 16-way set associative; With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: -
AngeloGioacchino Del Regno authored
This SoC features two clusters composed of: - 6x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 2x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 1MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: -
AngeloGioacchino Del Regno authored
This SoC features two clusters composed of: - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 2MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: -
AngeloGioacchino Del Regno authored
This SoC features two clusters composed of: - 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative, per-cpu 128KB L2 cache, 4-way set associative; - 4x Cortex A78: 64KB I-cache and 64KB D-cache, 4-way set associative, per-cpu 256KB L2 cache, 8-way set associative; Moreover, the two clusters are sharing a DSU L3 cache with size 2MB, 16-way set associative. With that in mind, add the appropriate properties needed to specify the caches information for this SoC, which will now be correctly exported to sysfs. Signed-off-by: -
Bernhard Rosenkränzer authored
Remove the unnecessary pins-are-numbered property from arm64 Mediatek DeviceTrees Signed-off-by:
Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by:
Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20221129023401.278780-6-bero@baylibre.comSigned-off-by:
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Chen-Yu Tsai authored
The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally. The 13 MHz clock is not a separate oscillator. Fix this by making the 13 MHz clock a divide-by-2 fixed factor clock, taking its input from the main 26 MHz oscillator. Fixes: 2e78620b ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by:
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Chen-Yu Tsai authored
The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8195 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 37f25828 ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by:
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Chen-Yu Tsai authored
The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8192 this divider is fixed to /2 and is not configurable. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 48489980 ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by:
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Chen-Yu Tsai authored
The systimer block derives its 13 MHz clock by dividing the main 26 MHz oscillator clock by 2 internally, not through the TOPCKGEN clock controller. On the MT8183 this divider is set either by power-on-reset or by the bootloader. The bootloader may then make the divider unconfigurable to, but can be read out by, the operating system. Making the systimer block take the 26 MHz clock directly requires changing the implementations. As an ABI compatible fix, change the input clock of the systimer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Fixes: 5bc8e287 ("arm64: dts: mt8183: add systimer0 device node") Signed-off-by:
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AngeloGioacchino Del Regno authored
Assign power domain to the U3PHY1 T-PHY in otder to keep this PHY alive after unused PD shutdown and to be able to completely cut and restore power to it, for example, to save some power during system suspend/sleep. Fixes: 2b515194 ("arm64: dts: mt8195: Add power domains controller") Signed-off-by:
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AngeloGioacchino Del Regno authored
Despite there being some flexibility regarding the P0/P1 connections, especially for TL and PERI, we must use P1 clocks on pcie1 otherwise we'll be dealing with unclocked access. Signed-off-by:
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Bernhard Rosenkränzer authored
Add bindings for the Mediatek mt8365-evk board. Signed-off-by:
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Hsin-Yi Wang authored
Kukui devices krane, kodana, and kakadu use detachable keyboards, which only have switches to be registered. Change the keyboard node's compatible of those boards to the newly introduced "google,cros-ec-keyb-switches", which won't include matrix properties. Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20220527045353.2483042-1-hsinyi@chromium.orgSigned-off-by:
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Allen-KH Cheng authored
Add dsi node for mt8186 SoC. Signed-off-by:
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Allen-KH Cheng authored
Add iommu and smi nodes for mt8186 SoC. Signed-off-by:
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Allen-KH Cheng authored
Add power domains controller for mt8186 SoC. Signed-off-by:
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- 25 Dec, 2022 1 commit
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Linus Torvalds authored
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