- 05 Nov, 2018 40 commits
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Andrey Grodzovsky authored
Start using drm_gpu_scheduler.ready isntead. v3: Add helper function to run ring test and set sched.ready flag status accordingly, clean explicit sched.ready sets from the IP specific files. v4: Add kerneldoc and rebase. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andrey Grodzovsky authored
Problem: A particular scheduler may become unsuable (underlying HW) after some event (e.g. GPU reset). If it's later chosen by the get free sched. policy a command will fail to be submitted. Fix: Add a driver specific callback to report the sched status so rq with bad sched can be avoided in favor of working one or none in which case job init will fail. v2: Switch from driver callback to flag in scheduler. v3: rebase v4: Remove ready paramter from drm_sched_init, set uncoditionally to true once init done. v5: fix missed change in v3d in v4 (Alex) Signed-off-by:
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Thomas Zimmermann authored
The content of drm_global.{c,h} is obsolete. v2: rebase on dropping TTM functionality Signed-off-by:Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Christian König authored
Make sure that the global BO state is always correctly initialized. This allows removing all the device code to initialize it. v2: fix up vbox (Alex) Signed-off-by:
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Christian König authored
As the name says we only need one global instance of ttm_bo_global. Just use a single exported instance which is save to initialize multiple times. Signed-off-by:
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Christian König authored
This way it can protect the whole BO global state. Signed-off-by:
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Christian König authored
As the name says we only need one global instance of ttm_mem_global. Drop all the driver initialization and just use a single exported instance which is initialized during BO global initialization. Signed-off-by:
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YueHaibing authored
Remove some duplicated include. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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YueHaibing authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/radeon/radeon_legacy_tv.c: In function 'radeon_legacy_tv_init_restarts': drivers/gpu/drm/radeon/radeon_legacy_tv.c:435:21: warning: variable 'pll' set but not used [-Wunused-but-set-variable] struct radeon_pll *pll; It never used since introduction in commit 4ce001ab ("drm/radeon/kms: add initial radeon tv-out support.") Also remove related variables 'dev, rdev, radeon_crtc' Signed-off-by:
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Oak Zeng authored
Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Yong Zhao authored
As part of the change, we stop taking the srbm lock, and start to use the same invalidation engine and software lock as amdgpu. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
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Yong Zhao authored
Add a flush_type parameter to that series of functions. Signed-off-by:
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Yong Zhao authored
Those register settings have been done in gfxhub_v1_0_program_invalidation() and mmhub_v1_0_program_invalidation(). Signed-off-by:
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Yong Zhao authored
The flags are added when calling amdgpu_gmc_pd_addr(). Signed-off-by:
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Yong Zhao authored
The same statement is later done in kgd_set_pasid_vmid_mapping(), so no need to do it in set_pasid_vmid_mapping(). Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Hardware support for Delta Color Compression (DCC) decompression is available in DC for GFX9 but there's no way for userspace to enable the feature. Enabling the feature can provide improved GFX performance and power savings in many situations. [How] Extend the GFX9 tiling flags to include DCC parameters. These are logically grouped together with tiling flags even if they are technically distinct. This trivially maintains backwards compatibility with existing users of amdgpu_gem_metadata. No new IOCTls or data structures are needed to support DCC. This patch helps expose DCC attributes to both libdrm and amdgpu_dm. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Fatemeh Darbehani authored
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Separate the set_hard_min_fclk_by_freq message from the SMU messages that are sent as part of pp_rv_set_display_requirement. directly notify min dcfclk to smu part 2 Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
[Why] TG in pipe_ctx stream resource is not null where used in commit_planes_do_stream_update since it is assigned the same time the stream is set in pipe_ctx - when the pipe is acquired. This null check produced a static code analysis warning and should be removed to avoid similar unnecessary checks in the future. [How] Remove the null check. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Rex Zhu authored
and vm_fini in amdgpu_driver_postclose_kms csa buffer will be created per ctx, when ctx fini, the csa buffer and va will be released. so need to do ctx_mgr fin before vm fini. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Hawking Zhang authored
Hard-code submission fence is not a sustainable way as there is more and more run-time psp kernel mode submission from driver to fw Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Amber Lin authored
Add amdgpu_amdkfd_ prefix to amdgpu functions served for amdkfd usage. v2: fix indentation Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Acked-by:
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Amber Lin authored
Remove unused function pointers in kfd2kgd structure. Signed-off-by:
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Amber Lin authored
After amdkfd module is merged into amdgpu, KFD can call amdgpu directly and no longer needs to use the function pointer. Replace those function pointers with functions if they are not ASIC dependent. Signed-off-by:
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Yong Zhao authored
Use the functions from amdgpu to avoid directly programming registers in amdgpu_amdkfd_gfx_v9.c. Signed-off-by:
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Yong Zhao authored
kfd has the same need to set the VM page table base register, so expose them for kfd to use for better maintainability. Signed-off-by:
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Yong Zhao authored
Those register settings have been performed in amdgpu initialization gfxhub_v1_0_setup_vmid_config() and mmhub_v1_0_setup_vmid_config(). So no need to do it again in kfd. Signed-off-by:
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Marek Olšák authored
Signed-off-by:
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Marek Olšák authored
This increases performance of compute queues. EOP events (PKT3_RELEASE_MEM) are stored into these buffers. Signed-off-by:
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Christian König authored
Signal a fault to the scheduler on an illegal instruction or register access violation instead of kicking of the reset handler directly. Signed-off-by:
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Christian König authored
Was never used. Signed-off-by:
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Christian König authored
Add a helper to immediately start timeout handling in case of a hardware fault. Signed-off-by:
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Christian König authored
Make sure we always restart the timer after a timeout and remove the device specific workarounds. Signed-off-by:
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John Clements authored
Revised comments in PSP SOS/Sysdriver loading sequence Signed-off-by:
John Clements <clements.jm@gmail.com> Signed-off-by:
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Philip Yang authored
For sdma v4, there is bug caused by commit d4e869b6b5d6 ("drm/amdgpu: add ring test for page queue")' local variable ring is reused and changed, so amdgpu_ttm_set_buffer_funcs_status(adev, true) is skipped accidently. As a result, amdgpu_fill_buffer() will fail, kernel message: [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.260444] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.260627] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.290119] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.290370] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.319971] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.320486] amdgpu 0000:19:00.0: [mmhub] VMC page fault (src_id:0 ring:154 vmid:8 pasid:32768, for process pid 0 thread pid 0) [ 25.320533] amdgpu 0000:19:00.0: in page starting at address 0x0000000000000000 from 18 [ 25.320563] amdgpu 0000:19:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00800134 Signed-off-by:Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Huang Rui authored
We add page queue for sdma to update page table. So here it also needs ring test to verify it workable during the initialization. Signed-off-by:
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Evan Quan authored
Since we see driver loading failure on Vega20. Keep it disabled until it's ready. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Alex Deucher authored
Don't use the paging queue on APUs. Tested-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Christian König authored
Only for testing, not sure if we should keep it like this. Signed-off-by:
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Christian König authored
Implement all the necessary stuff to get those extra rings working. Signed-off-by:
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