- 22 Nov, 2016 1 commit
-
-
git://linuxtv.org/snawrocki/samsungStephen Boyd authored
Pull Exynos5433 SoC updates from Sylwester Nawrocki: - addition of missing documentation and DT properties for the CMU_AUD block source clocks, - correction of CMU_FSYS parent clock definition, - marking as critical clocks which have to be enabled in order to access control registers of child CMUs. * tag 'clk-v4.10-exynos5433' of git://linuxtv.org/snawrocki/samsung: clk: exynos5433: Mark some clocks as critical clk: exynos5433: Add documentation for the audio block parent clocks clk: exynos5433: Fix parent clocks for FSYS block
-
- 18 Nov, 2016 1 commit
-
-
Marek Szyprowski authored
Some parent clocks of the Exynos5433 CMUs must be always enabled to access any register in the given CMU or devices connected to it. For the time being, until a proper solution based on runtime PM is applied, mark those clocks as critical (instead of ignore unused) to prevent disabling them. Reported-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com>
-
- 17 Nov, 2016 4 commits
-
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull more clk driver updates from Geert Uytterhoeven: - CSI2 and VIN clocks for R-Car M3-W, - Clock drivers for new RZ/G1M and RZ/G1E SoCs, - Minor bug fix for R-Car H3. * tag 'clk-renesas-for-v4.10-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add R8A7745 support clk: renesas: cpg-mssr: Add R8A7743 support clk: renesas: cpg-mssr: Add common R-Car Gen2 support clk: renesas: r8a7795: Fix HDMI parent clock clk: renesas: r8a7796: Add VIN clocks clk: renesas: r8a7796: Add CSI2 clocks
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geerty Uytterhoeven: - Add R-Car RST driver for obtaining mode pin state, and move the related functionality from platform code to DT, - Add r8a7743 and r8a7745 CPG Core Clock Definitions. The commits here are intermingled with arm-soc material because of the hard dependency we're breaking between mach code and driver code. We're replacing that with a driver dependency between the soc driver and the clk driver. * tag 'clk-renesas-for-v4.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (25 commits) clk: renesas: Add r8a7745 CPG Core Clock Definitions clk: renesas: Add r8a7743 CPG Core Clock Definitions clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init() clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init() clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init() ARM: shmobile: rcar-gen2: Stop passing mode pins state to clock driver ARM: shmobile: r8a7779: Stop passing mode pins state to clock driver ARM: shmobile: r8a7778: Stop passing mode pins state to clock driver clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins() clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driver clk: renesas: r8a7795: Obtain mode pin values from R-Car RST driver clk: renesas: rcar-gen2: Obtain mode pin values using RST driver clk: renesas: r8a7779: Obtain mode pin values from R-Car RST driver clk: renesas: r8a7778: Obtain mode pin values using R-Car RST driver arm64: renesas: r8a7796 dtsi: Add device node for RST module arm64: renesas: r8a7795 dtsi: Add device node for RST module ARM: dts: r8a7794: Add device node for RST module ARM: dts: r8a7793: Add device node for RST module ARM: dts: r8a7792: Add device node for RST module ARM: dts: r8a7791: Add device node for RST module ...
-
Marek Szyprowski authored
Audio block requires access to two parent clocks: audio PLL and oscillator, so add this information to device tree bindings documentation. Signed-off-by:
-
Marek Szyprowski authored
The proper parent clock for FSYS block is "aclk_fsys_200" according to the Exynos5433 reference manual. Signed-off-by:
-
- 16 Nov, 2016 7 commits
-
-
Stephen Boyd authored
Some checkpatch warnings about spaces were missed and we didn't mark two structs as static. Clean it up. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:Stephen Boyd <sboyd@codeaurora.org>
-
Stephen Boyd authored
Merge tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock changes from Maxime Ripard: The usual patches from us, but most notably the introduction of the A64 clocks unit. * tag 'sunxi-clk-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks clk: sunxi-ng: Add A64 clocks clk: sunxi-ng: Implement minimum for multipliers clk: sunxi-ng: Add minimums for all the relevant structures and clocks clk: sunxi-ng: Finish to convert to structures for arguments clk: sunxi-ng: Remove the use of rational computations clk: sunxi-ng: Rename the internal structures clk: sunxi: mod0: improve function-level documentation
-
Stephen Boyd authored
Merge tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clock updates from Shawn Guo: - A patch series to fix the long standing issue with glitchy parent mux of ldb_di_clk, which can hang up LVDS display when ipu_di_clk is sourced from ldb_di_clk. - A patch to add imx6ull clock support on top of imx6ul clock driver. * tag 'imx-clk-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: clk-imx6ul: add clk support for imx6ull clk: imx6: Fix procedure to switch the parent of LDB_DI_CLK clk: imx6: Make the LDB_DI0 and LDB_DI1 clocks read-only clk: imx6: Mask mmdc_ch1 handshake for periph2_sel and mmdc_ch1_axi_podf
-
Stephen Boyd authored
* clk-fixes: clk: efm32gg: Pass correct type to hw provider registration clk: berlin: Pass correct type to hw provider registration clk: sunxi: Fix M factor computation for APB1 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
-
Stephen Boyd authored
Merge tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-fixes Pull Allwinner clock fixes from Maxime Ripard: Two fixes, one for the old clock code, one for the new implementation. * tag 'sunxi-clk-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: clk: sunxi: Fix M factor computation for APB1 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent
-
Stephen Boyd authored
Dan Carpenter reports that we're passing a pointer to a pointer here when we should just be passing a pointer. Pass the right pointer so that the of_clk_hw_onecell_get() sees the appropriate data pointer on its end. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Fixes: 9337631f ("clk: efm32gg: Migrate to clk_hw based OF and registration APIs") Signed-off-by:
-
Stephen Boyd authored
Dan Carpenter reports that we're passing a pointer to a pointer here when we should just be passing a pointer. Pass the right pointer so that the of_clk_hw_onecell_get() sees the appropriate data pointer on its end. Reported-by:
-
- 15 Nov, 2016 4 commits
-
-
Leo Yan authored
In current kernel config 'CONFIG_STUB_CLK_HI6220' is disabled by default, as result stub clock driver has not been registered and CPUFreq driver cannot work. This patch is to enable stub clock driver in config for ARCH_HISI. Reported-by:
Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by:
Leo Yan <leo.yan@linaro.org> Signed-off-by:
-
Stephen Boyd authored
Merge tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: PLL initialization for PLLs having both an integral and fractional mode (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. * tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree clk: rockchip: add 400MHz to rk3066 clock rates table clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 clk: rockchip: add 533.25MHz to rk3399 clock rates table
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - SYS-DMAC, (H)SCIF, I2C, DRIF, and graphics related clocks for R-Car M3-W, - Minor fixes and cleanups. * tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add DU and LVDS clocks clk: renesas: r8a7796: Add VSP clocks clk: renesas: r8a7796: Add FCP clocks clk: renesas: cpg-mssr: Remove bogus commas from error messages clk: renesas: r8a7796: Add DRIF clock clk: renesas: cpg-mssr: Fix inverted debug check clk: renesas: rcar-gen3-cpg: Always use readl()/writel() clk: renesas: cpg-mssr: Always use readl()/writel() clk: renesas: r8a7796: Add I2C clocks clk: renesas: r8a7796: Add HSCIF clocks clk: renesas: r8a7796: Add SCIF clocks clk: renesas: r8a7796: Add SYS-DMAC clocks
-
Bai Ping authored
imx6ull is the derived SoC from imx6ul Signed-off-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Bai Ping <ping.bai@nxp.com> Signed-off-by:
Peter Chen <peter.chen@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
-
- 14 Nov, 2016 2 commits
-
-
Stephen Boyd authored
* clk-hisi: clk: hisilicon: add CRG driver for Hi3516CV300 SoC clk: hisilicon: add CRG driver for Hi3798CV200 SoC
-
Pan Wen authored
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by:
Pan Wen <wenpan@hisilicon.com> Signed-off-by:
Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by:
-
- 11 Nov, 2016 7 commits
-
-
Jiancheng Xue authored
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
Chen-Yu Tsai authored
The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks") Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
-
Chen-Yu Tsai authored
The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes: 5690879d ("clk: sunxi-ng: Add A23 CCU") Signed-off-by:
-
Stephen Boyd authored
* clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks
-
Georgi Djakov authored
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by:
Georgi Djakov <georgi.djakov@linaro.org> Acked-by:
-
Georgi Djakov authored
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.cSigned-off-by:
-
Georgi Djakov authored
Currently the RPM/RPM-SMD clock drivers do not register the xo clocks, so we should always add factor clock. When we later add xo clocks support into the drivers, we should update this function to skip registration. By doing so we avoid any DT dependencies. Signed-off-by:
-
- 10 Nov, 2016 8 commits
-
-
Stephen Boyd authored
* clk-qcom-8994: clk: qcom: Add support for msm8994 global clock controller dt-bindings: qcom: clocks: Add msm8994 clock bindings
-
Bastian Köcher authored
The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by:
Bastian Köcher <mail@kchr.de> [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by:
Jeremy McNicoll <jeremymc@redhat.com> [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by:
-
Jeremy McNicoll authored
Signed-off-by:
-
Wei Yongjun authored
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
-
Sergei Shtylyov authored
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be>
-
Sergei Shtylyov authored
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by:
-
Sergei Shtylyov authored
Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module Standby and Software Reset support code, using the CPG/MSSR driver core. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by:
-
Stephen Boyd authored
The clocks on these boards run at 25 MHz, not 19.2 and 27 like other platforms. Unfortunately I copy/pasted from other similar SoCs but forgot this one is different. Fix it. Fixes: a085f877 ("clk: qcom: Move cxo/pxo/xo into dt files") Signed-off-by:
-
- 09 Nov, 2016 3 commits
-
-
Stephen Boyd authored
This function is passed an __iomem pointer but we use a u32 pointer instead which makes checkers like spare complain. Furthermore, "lock" is a pretty poor variable name for a string that will go into lockdep reports and the symbol isn't marked static. Cleanup all this. Acked-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
-
Uwe Kleine-König authored
The : of the ?: operator should have a leading space. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [sboyd@codeaurora.org: Also remove useless parenthesis] Signed-off-by:
-
Arnd Bergmann authored
The new pxa2xx_determine_rate() function seems lacking in a few regards: - For an exact match or no match at all, the rate is uninitialized as reported by gcc -Wmaybe-unintialized: drivers/clk/pxa/clk-pxa.c: In function 'pxa2xx_determine_rate': drivers/clk/pxa/clk-pxa.c:243:5: error: 'rate' may be used uninitialized in this function - If we get a non-exact match, the req->rate output is never set to the actual rate but remains at the requested rate. - We should not attempt to print a rate if none could be found This rewrites the logic accordingly. Fixes: 9fe69429 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
-
- 08 Nov, 2016 3 commits
-
-
Shunli Wang authored
In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by:
Shunli Wang <shunli.wang@mediatek.com> Signed-off-by:
James Liao <jamesjj.liao@mediatek.com> Signed-off-by:
Erin Lo <erin.lo@mediatek.com> Tested-by:
John Crispin <blogic@openwrt.org> Acked-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
-
Shunli Wang authored
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by:
-
Arnd Bergmann authored
The dummy_clk_set_parent function is marked as 'static' but is no longer referenced from the pxa25x clk driver after the last use of the RATE_RO_OPS() macro is gone from this file, causing a harmless build warning: In file included from drivers/clk/pxa/clk-pxa25x.c:24:0: drivers/clk/pxa/clk-pxa.h:146:12: error: 'dummy_clk_set_parent' defined but not used [-Werror=unused-function] This marks the functon as 'inline', which lets the compiler simply drop it when it gets referenced. Fixes: 9fe69429 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq") Signed-off-by:
-
