- 13 Apr, 2021 1 commit
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Tudor Ambarus authored
The slew rate was enabled by default for each configuration of the pin. In case the pin had more than one configuration, even if we set the slew rate as disabled in the device tree, the next pin configuration would set again the slew rate enabled by default, overwriting the slew rate disablement. Instead of enabling the slew rate by default for each pin configuration, enable the slew rate by default just once per pin, regardless of the number of configurations. This way the slew rate disablement will also work for cases where pins have multiple configurations. Fixes: c709135e ("pinctrl: at91-pio4: add support for slew-rate") Signed-off-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by:
Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 10 Apr, 2021 1 commit
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Krzysztof Kozlowski authored
The Special Function Registers on all Exynos SoC, including ARM64, are 32-bit wide, so entire driver uses matching functions like readl() or writel(). On 64-bit ARM using unsigned long for register masks: 1. makes little sense as immediately after bitwise operation it will be cast to 32-bit value when calling writel(), 2. is actually error-prone because it might promote other operands to 64-bit. Addresses-Coverity: Unintentional integer overflow Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20210408195029.69974-1-krzysztof.kozlowski@canonical.comSigned-off-by:
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- 08 Apr, 2021 9 commits
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Guru Das Srinagesh authored
Add support for the two GPIOs present on Qualcomm Technologies, Inc. PM8008. Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Guru Das Srinagesh <gurus@codeaurora.org> Link: https://lore.kernel.org/r/129d241ee510e28536d35dbfeee75474e12d8d22.1617901945.git.gurus@codeaurora.orgSigned-off-by:
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Guru Das Srinagesh authored
Add support for the 2 GPIOs present on Qualcomm Technologies, Inc. PM8008. Acked-by:
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Niklas Söderlund authored
The error is constructed using the wrong variable. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210328164222.720525-1-niklas.soderlund+renesas@ragnatech.seSigned-off-by:
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Fabio Estevam authored
Performing the 'unbind' operation on pinctrl drivers is not a sensible usecase, so pass the suppress_bind_attrs atribute to prevent it. Signed-off-by:
Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210328183034.555702-2-festevam@gmail.comSigned-off-by:
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Fabio Estevam authored
i.MX is a DT-only platform, so of_match_ptr() can be safely removed. Remove the unneeded of_match_ptr(). Signed-off-by:
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Junlin Yang authored
when devm_kcalloc fails, use -ENOMEM instead of -EINVAL, and consistent with other devm_kcalloc return values. Signed-off-by:
Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210330062655.1027-1-angkery@163.comSigned-off-by:
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Jianqun Xu authored
RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports set iomux, pull, drive strength and schmitt. Signed-off-by:
Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20210319081441.368358-1-jay.xu@rock-chips.comSigned-off-by:
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Marek Vasut authored
The "invalid function %d on pin %d .\n" message is triplicated in the driver in different variants, just pull it into the function and have it once in the driver. The bonus is that all variants of the message now print the pin number and AF consistently, so it is easier to debug such pinmux problems. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabien Dessenne <fabien.dessenne@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by:
Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210406180035.279249-1-marex@denx.deSigned-off-by:
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Randy Dunlap authored
The additional patch below fixes all of the kconfig warnings and build errors for me. Link: https://lore.kernel.org/r/9e1cec76-1c0a-9203-7995-4c2d09b711d8@infradead.orgSigned-off-by:
Randy Dunlap <rdunlap@infradead.org> [Tweaked some other line in the BCMxxx] Signed-off-by:
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- 07 Apr, 2021 1 commit
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Linus Walleij authored
Merge tag 'renesas-pinctrl-for-v5.13-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.13 (take two) - Add bias support for the R-Car M2-W and M2-N, and RZ/G1M and RZ/G1N SoCs, - Miscellaneous cleanups and improvements.
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- 31 Mar, 2021 2 commits
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Linus Walleij authored
Add depends on OF so we don't get weird build errors on randconfig. Also order selects the same as the other drivers for pure aestetic reasons. Reported-by:
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Álvaro Fernández Rojas authored
The current implementation of bcm6362_set_gpio() produces the following warning on x86_64: drivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio': drivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 503 | (uint32_t) desc->drv_data, 0); | ^ Modify the code to make it similar to bcm63268_set_gpio() in order to fix the warning. Fixes: 705791e2 ("pinctrl: add a pincontrol driver for BCM6362") Signed-off-by:Álvaro Fernández Rojas <noltari@gmail.com> Link: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.comReviewed-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
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- 29 Mar, 2021 25 commits
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Linus Walleij authored
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Linus Walleij authored
Merge tag 'intel-pinctrl-v5.13-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.13-1 * Don't disable disabled IRQs in the handler * Fix the base calculation for groups defined by size The following is an automated git shortlog grouped by driver: intel: - No need to disable IRQs in the handler - Show the GPIO base calculation explicitly
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Wan Jiabing authored
linux/io.h has been included at line 6, so remove the duplicate include at line 18. Signed-off-by:
Wan Jiabing <wanjiabing@vivo.com> Reviewed-by:
Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210323013727.135571-1-wanjiabing@vivo.comSigned-off-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs to different functions. BCM6318 is similar to BCM6328 with the addition of a pad register, and the GPIO meaning of the mux register changes based on the GPIO number. Co-developed-by:
Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6318 SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210324081923.20379-22-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6318 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs to different functions. Depending on the mux, these are either single pin configurations or whole pin groups. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM63268 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in the BCM63268 family SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32 GPIOs onto alternative functions. Not all are documented. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6368 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6368 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincotrol driver for BCM6362. BCM6362 allows muxing individual GPIO pins to the LED controller, to be available by the integrated wifi, or other functions. It also supports overlay groups, of which only NAND is documented. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6362 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6362 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincotrol driver for BCM6358. BCM6358 allow overlaying different functions onto the GPIO pins. It does not support configuring individual pins but only whole groups. These groups may overlap, and still require the directions to be set correctly in the GPIO register. In addition the functions register controls other, not directly mux related functions. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6358 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6358 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as GPIOs, as LEDs for the integrated LED controller, or various other functions. Its pincontrol mux registers also control other aspects, like switching the second USB port between host and device mode. Co-developed-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the GPIO sysctl found in BCM6328 SoCs. Signed-off-by:
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Álvaro Fernández Rojas authored
Add binding documentation for the pincontrol core found in BCM6328 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
Add a helper for registering BCM63XX pin controllers. Co-developed-by:
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Álvaro Fernández Rojas authored
Convert existing BCM6345 GPIO binding documentation to YAML and add binding documentation for the GPIO controller found in BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 SoCs. Co-developed-by:
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Álvaro Fernández Rojas authored
This is needed for properly registering GPIO regmap as a child of a regmap pin controller. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com> Link: https://lore.kernel.org/r/20210324081923.20379-3-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
The current code doesn't check if GPIOLIB_IRQCHIP is enabled, which results in a compilation error when trying to build gpio-regmap if CONFIG_GPIOLIB_IRQCHIP isn't enabled. Fixes: 6a45b0e2 ("gpiolib: Introduce gpiochip_irqchip_add_domain()") Suggested-by:
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- 25 Mar, 2021 1 commit
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Andy Shevchenko authored
In IRQ handler interrupts are already disabled, hence no need to repeat it. Even in the threaded case, which is disabled here, it is not a problem because IRQ framework serializes descriptor handling. Remove disabling IRQ part in the handler. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com>
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