- 10 Apr, 2024 40 commits
-
-
Wenjing Liu authored
[why] Move built test pattern as part of pipe resource update for odm to ensure we rebuild test pattern params every time we have an ODM update Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Joshua Aberback authored
[Why] Future implementations will require a distinction between AC power and DC power (wall power and battery power, respectively). To accomplish this, adding a power mode parameter to certain dc interfaces, and adding a separate DML2 instance for DC mode validation. Default behaviour unchanged. Reviewed-by:
Jun Lei <jun.lei@amd.com> Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
-
Joshua Aberback authored
[Why] When the DML2 wrapper explicitly accesses context->dml2, that creates a dependency on where dc saves the DML object. This dependency makes it harder to have multiple co-existing DML objects, which we would like to have for upcoming functionality. [How] - make all DML21 interfaces take in a DML2 object as parameter - remove all references to context->dml2, use parameter instead Reviewed-by:
-
Alvin Lee authored
[Description] - Add logging for first DMUB inbox message that timed out to diagnostic data - It is useful to track the first failed message for debug purposes because once DMUB becomes hung (typically on a message), it will remain hung and all subsequent messages. In these cases we're interested in knowing which is the first message that failed. Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
-
Xi (Alex) Liu authored
[Why and how] External display has corruption because no root clock control function. Add the function pointer to fix the issue. Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Xi (Alex) Liu <xi.liu@amd.com> Signed-off-by:
-
Nicholas Kazlauskas authored
[Why] The threshold is no longer useful for blocking suboptimal power states for DCN35 based on real measurement. [How] Reduce to the minimum threshold duration, 1us. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Acked-by:
-
Alvin Lee authored
[Description] Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL, OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for more debuggability for a system crash. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
-
Leo (Hanghong) Ma authored
[Why && How] OTG can be disabled before setting dpms on. Add check to skip wait when setting AV mute if OTG is disabled. Reviewed-by:
Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by:
-
Alex Hung authored
[WHY] dynamic memory safety error detector (KASAN) catches and generates error messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not support certain features which are not initialized. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3199Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
-
Duncan Ma authored
[Why] HPO can be power gated unconditionally for DCN35. [How] Set disable flag to false. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
-
Daniel Miess authored
[Why & How] Enable root clock optimization for HDMISTREAMCLK and only disable it when it's actively being used. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
-
George Shen authored
[Why/How] Some issues may require a trace of the previous SMU messages from DC to understand the context and aid in debugging. Actual logging to be implemented when needed. Reviewed-by:
-
Sung Joon Kim authored
[why] As per programming guide, we need to enable the virtual pixel clock via DTBCLK DTO and ungate the clock before we begin programming OPP/OPTC control registers. Otherwise, the double-buffered registers will be left pending until the clocks are enabled. [how] Move the DTBCLK DTO programming up to where we do the legacy DP DTO programming. Reviewed-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
-
Wenjing Liu authored
[why] There is an ambiguity in subvp pipe topology log. The log doesn't show subvp relation to main stream and it is not clear that certain stream is an internal stream for subvp pipes. [how] Separate subvp pipe topology logging from main pipe topology. Log main stream indices instead of the internal stream for subvp pipes. The following is a sample log showing 2 streams with subvp enabled on both: pipe topology update ________________________ | plane0 slice0 stream0| |DPP1----OPP1----OTG1----| | plane0 slice0 stream1| |DPP0----OPP0----OTG0----| | (phantom pipes) | | plane0 slice0 stream0| |DPP3----OPP3----OTG3----| | plane0 slice0 stream1| |DPP2----OPP2----OTG2----| |________________________| Reviewed-by:
-
Dillon Varone authored
[WHY&HOW] Update dmub and driver interface for future FAMS revisions. Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
-
Danijel Slivka authored
Apply this rule to all newer asics in sriov case. For asic with VF MMIO access protection avoid using CPU for VM table updates. CPU pagetable updates have issues with HDP flush as VF MMIO access protection blocks write to BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL register during sriov runtime. Moved the check to amdgpu_device_init() to ensure it is done after amdgpu_device_ip_early_init() where the IP versions are discovered. Signed-off-by:
Danijel Slivka <danijel.slivka@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
-
Arunpravin Paneer Selvam authored
Enable pipe1 support starting from SIENNA CICHLID asic Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2117Reviewed-by:
Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by:
ZhenGuo Yin <zhenguo.yin@amd.com> Signed-off-by:
-
ZhenGuo Yin authored
Use correct ref/mask for differnent gfx ring pipe. This should fix the gfx hang issue after enabling gfx pipe1. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2117Reviewed-by:
-
Joshua Aberback authored
[Why] The function to count the number of valid connectors does not guarantee that the first n indices are valid, only that there exist n valid indices. When invalid indices are present, this results in later valid connectors being missed, as processing would end after checking n indices. [How] - count valid indices separately from total indices examined - add explicit definition of MAX_LINKS Reviewed-by:
-
Hersen Wu authored
[Why] Mst slot nums equals to pbn / pbn_div. Today, pbn_div refers to dm_mst_get_pbn_divider -> dc_link_bandwidth_kbps. In dp_link_bandwidth_kbps, which includes effect of FEC overhead already. As result, we should not include effect of FEC overhead again while calculating pbn by kpbs_to_peak_pbn (stream_kbps). [How] Include FEC overhead within dp_link_bandwidth_kbps. Remove FEC overhead from kbps_to_peak_pbn. Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
-
Tao Zhou authored
SDMA_CNTL is not set in some cases, driver configures it by itself. v2: simplify code Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
-
Leon Huang authored
[Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Leon Huang <leon.huang1@amd.com> Tested-by:
-
Daniel Miess authored
[Why] With root clock optimization now enabled for DCN35 there are still RCO registers still not being toggled [How] Add in logic to toggle RCO registers for DPPCLK, DPSTREAMCLK and DSCCLK Reviewed-by:
-
Wenjing Liu authored
[why] There could be cases that we are transition from MPC to ODM combine. In this case if we map pipes before unmapping MPC pipes, we might temporarly run out of pipes. The change reorders pipe resource allocation. So we unmapping pipes before mapping new pipes. Reviewed-by:
-
Samson Tam authored
[Why] In two display configuration, switching between subvp and non-subvp may cause underflow because it moves an existing pipe between displays [How] Create helper function for applying pipe split flags Apply pipe split flags prior to deciding on subvp During subvp check, do not merge pipes, so it can retain previous pipe configuration Add check for prev odm pipe in subvp check For single display subvp case, use same odm policy for phantom pipes as main subvp pipe Reviewed-by:
-
Hersen Wu authored
[Why] Mode pbn is not calculated correctly because timing pixel encoding is not checked within convert_dc_color_depth_into_bpc. [How] Get mode kbps from dc_bandwidth_in_kbps_from_timing, then calculate pbn by kbps_to_peak_pbn. Reviewed-by:
-
Mounika Adhuri authored
[why & how] Modified definitions of 1 function and 2 structs to remove warnings on certain specific compiler configurations due to redefinition. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Mounika Adhuri <moadhuri@amd.com> Tested-by:
-
Yifan Zhang authored
This patch to add smu 14.0.1 support Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
-
lima1002 authored
update ppsmc.h pmfw.h and driver_if.h for smu v14_0_1 Reviewed-by:
lima1002 <li.ma@amd.com> Signed-off-by:
-
shaoyunl authored
From MES version 0x54, the log entry increased and require the log buffer size to be increased. The 16k is maximum size agreed Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Acked-by:
-
Alex Deucher authored
Covers GPU page fault debugging and adds a reference to umr. v2: update client ids to include SQC/G v3: Remove duplicate text v4: add umr documentation link, fix typo Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
-
shaoyunl authored
The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by:
-
Tim Huang authored
While doing multiple S4 stress tests, GC/RLC/PMFW get into an invalid state resulting into hard hangs. Adding a GFX reset as workaround just before sending the MP1_UNLOAD message avoids this failure. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Acked-by:
-
Yang Wang authored
refine function signature of amdgpu_aca_get_error_data(); Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
-
Li Ma authored
There is a new DCN veriosn 3.5.1 need to load Signed-off-by:
-
Lijo Lazar authored
For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got aborted. In such cases, reset the device during resume phase. This is a workaround till a proper solution is finalized. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
-
Sunil Khatri authored
Add FW information of all the IP's in the devcoredump. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
-
Lang Yu authored
Otherwise the old one will be used during GPU reset. That's not expected. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Reviewed-by:
-
Lijo Lazar authored
Downgrade to debug information when IBs are skipped. Also, use dev_* to identify the device. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
-
Yang Wang authored
v1: add a new enumeration type to identify device attribute node, this method is relatively more efficient compared with 'strcmp' in update_attr() function. v2: rename device_attr_type to device_attr_id. Signed-off-by:
Ma Jun <majun@amd.com> Reviewed-by:
-
