- 12 Feb, 2024 38 commits
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Alex Deucher authored
MEM_TRAINING_ENCROACHED_SIZE is for BIST training data. It's not memory type specific. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hamza Mahfooz authored
Currently, if the abmlevel module parameter is set, it is possible for user space to override the ABM level at some point after boot. However, that is undesirable because it means that we aren't respecting the user's wishes with regard to the level that they want to use. So, prevent user space from changing the ABM level if the module parameter is set to a non-auto value. Tested-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Nikita Zhandarovich authored
Since 'adev->dm.dc' in amdgpu_dm_fini() might turn out to be NULL before the call to dc_enable_dmub_notifications(), check beforehand to ensure there will not be a possible NULL-ptr-deref there. Also, since commit 1e88eb1b ("drm/amd/display: Drop CONFIG_DRM_AMD_DC_HDCP") there are two separate checks for NULL in 'adev->dm.dc' before dc_deinit_callbacks() and dc_dmub_srv_destroy(). Clean up by combining them all under one 'if'. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 81927e28 ("drm/amd/display: Support for DMUB AUX") Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Nikita Zhandarovich authored
Clean up a typo in pr_err() erroneously printing NI MC 'rdev->mc_fw->size' during SMC firmware load. Log 'rdev->smc_fw->size' instead. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 6596afd4 ("drm/radeon/kms: add dpm support for btc (v3)") Signed-off-by:
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Sonny Jiang authored
Enable support for jpeg_v5_0_0 ip block. Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Sonny Jiang authored
Add doorbell for JPEG5 Signed-off-by:
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Sonny Jiang authored
Add PG support for JPEG5 Signed-off-by:
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Srinivasan Shanmugam authored
when 'find_dcfclk_for_voltage()' function is looping over VG_NUM_SOC_VOLTAGE_LEVELS (which is 8), but the size of the DcfClocks array is VG_NUM_DCFCLK_DPM_LEVELS (which is 7). When the loop variable i reaches 7, the function tries to access clock_table->DcfClocks[7]. However, since the size of the DcfClocks array is 7, the valid indices are 0 to 6. Index 7 is beyond the size of the array, leading to a buffer overflow. Reported by smatch & thus fixing the below: drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.c:550 find_dcfclk_for_voltage() error: buffer overflow 'clock_table->DcfClocks' 7 <= 7 Fixes: 3a83e4e6 ("drm/amd/display: Add dcn3.01 support to DC (v2)") Cc: Roman Li <Roman.Li@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
'max_chunks_fbc_mode' is only declared and assigned a value under a specific condition in the following lines: if (data->fbc_en[i] == 1) { max_chunks_fbc_mode = 128 - dmif_chunk_buff_margin; } If 'data->fbc_en[i]' is not equal to 1 for any i, max_chunks_fbc_mode will not be initialized if it's used outside of this for loop. Ensure that 'max_chunks_fbc_mode' is properly initialized before it's used. Initialize it to a default value right after its declaration to ensure that it gets a value assigned under all possible control flow paths. Thus fixing the below: drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dce_calcs.c:914 calculate_bandwidth() error: uninitialized symbol 'max_chunks_fbc_mode'. drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dce_calcs.c:917 calculate_bandwidth() error: uninitialized symbol 'max_chunks_fbc_mode'. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Cc: Harry Wentland <harry.wentland@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: -
Srinivasan Shanmugam authored
wait_time_microsec = max(wait_time_microsec, (uint32_t) DPIA_CLK_SYNC_DELAY); Above line is trying to assign the maximum value between 'wait_time_microsec' and 'DPIA_CLK_SYNC_DELAY' to wait_time_microsec. However, 'wait_time_microsec' has not been assigned a value before this line, initialize 'wait_time_microsec' at the point of declaration. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_dpia.c:697 dpia_training_eq_non_transparent() error: uninitialized symbol 'wait_time_microsec'. Fixes: 630168a9 ("drm/amd/display: move dp link training logic to link_dp_training") Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Sonny Jiang authored
Add support for JPEG5 Signed-off-by:
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Sonny Jiang authored
Enable support for vcn_v5_0_0_ip_block Signed-off-by:
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Dan Carpenter authored
These ANDs should be ORs or it will lead to a NULL dereference. Fixes: fb5a3d03 ("drm/amd/display: Add NULL test for 'timing generator' in 'dcn21_set_pipe()'") Fixes: 886571d2 ("drm/amd/display: Fix 'panel_cntl' could be null in 'dcn21_set_backlight_level()'") Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Hamza Mahfooz authored
We have observed that there are quite a number of PSR-SU panels on the market that are unable to keep up with what user space throws at them, resulting in hangs and random black screens. So, make damage clips support configurable and disable it by default for PSR-SU displays. Cc: stable@vger.kernel.org Reviewed-by:
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Sonny Jiang authored
Add VCN_5_0_0 IP init, ring functions, DPG support. v2: squash in warning fixes (Alex) v3: squash in block and ring init, boot, doorbell enablement, DPG support (Alex) Signed-off-by: -
Sonny Jiang authored
Add VCN5_0_0 firmware support Signed-off-by:
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Hawking Zhang authored
v1: Add vcn v5_0_0 register offset and shift masks header files. (Hawking) v2: Update vcn v5_0_0 register offset and shift masks header files to RE2. (Likun) v3: Update vcn v5_0_0 register offset and shift masks header files to RE2.5. (Likun) v4: Update vcn v5_0_0 register offset and shift masks header files to RE3. (Likun) v5: Clean up vcn v5_0_0 ip headers. (Alex) Signed-off-by:Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Likun Gao authored
Add hdp v7_0 ip block Signed-off-by:
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Likun Gao authored
Add hdp v7_0 ip block support. Signed-off-by:
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Hawking Zhang authored
v1: Add hdp v7_0_0 register offset and shift masks header files (Hawking) v2: Update hdp v7_0_0 register offset and shift masks header files for RE2.5 (Likun) v3: Clean up hdp v7_0_0 ip headers (Alex) Signed-off-by: -
Likun Gao authored
Add ih v7_0 ip block. Signed-off-by:
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Likun Gao authored
Add ih v7_0 ip block support. Signed-off-by:
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Saleemkhan Jamadar authored
Jpeg DPG support for GC IP v11_5_0 Signed-off-by:
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by:
Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com> Signed-off-by:
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Saleemkhan Jamadar authored
add ucode id and cmd buffer for jpeg psp sram programming and Jpeg DPG support. Signed-off-by:
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Hawking Zhang authored
v1: Add osssys v7_0_0 register offset and shift masks header files. (Hawking) v2: Update osssys v7_0_0 register offset and shift masks header files to RE2. (Likun) v3: Update osssys v7_0_0 register offset and shift masks header files to RE2.5. (Likun) v4: Clean up osssys v7_0_0 ip headers (Alex) Signed-off-by: -
Likun Gao authored
Add lsdma v7_0 ip block. v2: squash in updates (Alex) Signed-off-by:
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Likun Gao authored
Add lsdma v7_0 ip block support. Signed-off-by:
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Hawking Zhang authored
v1: Add lsdma v7_0_0 register offset and shift masks header files (Hawking) v2: Update lsdma v7_0_0 register offset and shift masks header files for RE2.5 (Likun) v3: Clean up lsdma v7_0_0 ip headers (Alex) Signed-off-by: -
Yang Wang authored
send smu rma reason event to smu in ras eeprom driver. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
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Yang Wang authored
implement smu send rma reason function for smu v13.0.6 Signed-off-by:
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Hawking Zhang authored
Add athub v4_1_0 ip block support. v2: fix clang warning (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add athub v4_1_0 register offset and shift masks header files. (Hawking) v2: Update athub v4_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update athub v4_1_0 register offset and shift masks header files to RE2.5 (Likun) v4: Update athub v4_1_0 register offset and shift masks header files to RE3. (Likun) v5: Clean up athub v4_1_0 ip headers. (Alex) Signed-off-by: -
Likun Gao authored
Support to set fw_load_type=3 to use backdoor rlc autoload. Signed-off-by:
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Likun Gao authored
Skip ucode BO reservation for backdoor RLC autoload. Signed-off-by:
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Likun Gao authored
Only enable VCN/JPEG dpm when VCN/JPEG PG flag was set when smu set dpm table. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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Kent Russell authored
Its currently incorrectly multiplied by number of XCCs in the partition Fixes: be457b22 ("drm/amdkfd: Update cache info for GFX 9.4.3") Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Laurent Morichetti authored
Call the 2nd level trap handler if the cwsr handler is entered with any one of wave_start, wave_end, or trap_after_inst exceptions. Signed-off-by:
Laurent Morichetti <laurent.morichetti@amd.com> Tested-by:
Lancelot Six <lancelot.six@amd.com> Reviewed-by:
Jay Cornwall <jay.cornwall@amd.com> Acked-by:
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Jonathan Kim authored
The debugger requires the control stack header to be filled in to update_waves. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Signed-off-by:
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- 07 Feb, 2024 2 commits
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Lijo Lazar authored
HDP flush remapping is not done for VFs. Keep the original offsets in VF environment. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Srinivasan Shanmugam authored
'stream_enc_regs' array is an array of dcn10_stream_enc_registers structures. The array is initialized with four elements, corresponding to the four calls to stream_enc_regs() in the array initializer. This means that valid indices for this array are 0, 1, 2, and 3. The error message 'stream_enc_regs' 4 <= 5 below, is indicating that there is an attempt to access this array with an index of 5, which is out of bounds. This could lead to undefined behavior Here, eng_id is used as an index to access the stream_enc_regs array. If eng_id is 5, this would result in an out-of-bounds access on the stream_enc_regs array. Thus fixing Buffer overflow error in dcn301_stream_encoder_create reported by Smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn301/dcn301_resource.c:1011 dcn301_stream_encoder_create() error: buffer overflow 'stream_enc_regs' 4 <= 5 Fixes: 3a83e4e6 ("drm/amd/display: Add dcn3.01 support to DC (v2)") Cc: Roman Li <Roman.Li@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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