- 19 Dec, 2013 5 commits
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Simon Horman authored
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Simon Horman authored
Linux 3.13-rc3 Conflicts: drivers/pinctrl/sh-pfc/pfc-r8a7740.c drivers/pinctrl/sh-pfc/pfc-sh7372.c
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Simon Horman authored
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Simon Horman authored
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Simon Horman authored
This is a commit from the for-next branch of Linus Walleij's pin control tre git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git It is the oldest commit in that branch that provides the dependencies needed for SoC changes to the usage of sh-pfc.
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- 18 Dec, 2013 1 commit
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Laurent Pinchart authored
Prepare the clock at probe time, as there is no other appropriate place in the driver where we're allowed to sleep. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org>
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- 14 Dec, 2013 2 commits
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Laurent Pinchart authored
Turn clk_enable() and clk_disable() calls into clk_prepare_enable() and clk_disable_unprepare() to get ready for the migration to the common clock framework. Signed-off-by:
Magnus Damm <damm@opensource.se> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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Laurent Pinchart authored
The break timer accesses hardware registers and thus requires the port to be enabled. It currently ensures this by enabling the port at the beginning of the timer handler, and disabling it at the end. However, the enable/disable operations call the runtime PM sync functions, which are not allowed in atomic context. The current situation is thus broken. This change relies on non-atomic code to enable/disable the port. The break timer will only be started from the IRQ handler, which already runs with the port enabled. We just need to ensure that the port won't be disabled with the timer running, and that's easily done by just cancelling the timer in the port disable function. Signed-off-by:
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- 13 Dec, 2013 3 commits
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Laurent Pinchart authored
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated. Those clocks are found on Renesas ARM SoCs. Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Laurent Pinchart authored
DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by:
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Laurent Pinchart authored
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are too custom to be supported in a generic driver. Those clocks can be divided in two categories: - Fixed rate clocks with multiplier and divisor set according to boot mode configuration - Custom divider clocks with SoC-specific divider values This driver supports both. Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
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- 12 Dec, 2013 13 commits
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Laurent Pinchart authored
On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Laurent Pinchart authored
There's more than one window, name the field windows. Signed-off-by:
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Laurent Pinchart authored
This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by:
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Laurent Pinchart authored
The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by:
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Laurent Pinchart authored
0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by:
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Laurent Pinchart authored
Some indices take positive values only, make them unsigned. Signed-off-by:
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Alexandre Belloni authored
ops->pin_config_get() is only used in one specific path that will only be taken for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf by using debugfs. By removing the check in pinconf_check_ops(), let's stop pressuring people to write a pin_config_get() function that will never be used and so will probably never be tested. Removing the check in pinconf_pins_show() allows driver to not implement pin_config_get() but still get a dump of the pinconf in debugfs by implementing pin_config_dbg_show(). Finally, not implementing pin_config_get() now results in returning -ENOTSUPP instead of -EINVAL. While this doesn't have any real impact for now, this feels more right. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by:
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Alexandre Belloni authored
When passing a not initialized config parameter, at91_pinconf_get() would return a bogus value. Fix that by initializing it to zero before using it. Signed-off-by:
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Alexandre Belloni authored
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Laurent Pinchart authored
The board has 7 buttons connected to GPIOs, add a corresponding gpio-keys device. Signed-off-by:
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Laurent Pinchart authored
Use the %zu and %pad printk specifiers to print size_t and dma_addr_t variables, and cast pointers to uintptr_t instead of unsigned int where applicable. This fixes warnings on platforms where pointers and/or dma_addr_t have a different size than int. Cc: linux-serial@vger.kernel.org Signed-off-by:
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Kuninori Morimoto authored
This patch support FSI-AK4648 with simple audio card Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
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- 11 Dec, 2013 2 commits
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Linus Walleij authored
We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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- 10 Dec, 2013 14 commits
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Valentine Barshak authored
There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by:
Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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Valentine Barshak authored
Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by:
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Valentine Barshak authored
This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by:
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Valentine Barshak authored
This groups VIN0 HSYNC and VSYNC pins together since one cannot be used without another. Signed-off-by:
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Valentine Barshak authored
This drops superfluous "signal" word from the pin group names and renames data_enable group to clkenb as in the h/w manual. Signed-off-by:
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Takashi Yoshii authored
SH_PFC_PIN_GROUP(), pins[], mux[], defines clk, sync, ss1, ss2, rx, tx But, msiof?_groups[] defines clk, ctrl, data Fix msiof[012]_groups members to be consistent to PIN_GROUP. Signed-off-by:
Takashi Yoshii <takasi-y@ops.dti.ne.jp> Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Laurent Pinchart authored
The macro is defined identically in four different locations. Share it. Signed-off-by:
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Linus Walleij authored
We had a compilation failure on x86_64 due to missing OF support as this was an implicit dependency. Add an explicit dependency on OF and OF_IRQ on the SoC driver. Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: -
Simon Horman authored
Based on work for the bockw board by Kuninori Morimoto. Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: -
Simon Horman authored
Based on work for the r8a7778 SoC by Kuninori Morimoto. Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: -
Magnus Damm authored
Add "renesas,intc-irqpin-r8a7779" to the compatible string for the IRQ pins in case of r8a7779 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by:
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Magnus Damm authored
Add "renesas,intc-irqpin-r8a7778" to the compatible string for the IRQ pins in case of r8a7778 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by:
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