Instead of using break, this one bubbles down into the kernel
	directly.  This code works, but isn't performance optimal yet.

	didn't preserve b6 and r11 anymore.  Unfortunately, preserving them costs
	a few cycles (~5 cycles in the cached case).  The uncached case is hopefully
	mostly unaffected because the number of cache-lines touched is the same
	(without preserving b6 and r11, the entry-patch _almost_ got away with
	touching a single 128-byte cacheline, but not quite, because r8 also
	had to be initialized).

	now cleared by the syscall exit path.

	whitespace changes only.

	Fix setting of current->thread.on_ustack flag in optimized syscall exit path.
	Tune break_fault for syscall execution.
	Break ia32_execve: the ia64_execve() hack that was there is too ugly for
	words; surely we can do better...

Here's another sn2 update.  It includes a bunch of misc. bits:
  o a bunch of cleanup from hch
  o addition of DMA routine wrappers
  o update of other PCI routines
  o topology.h prototype addition.

This should get the CONFIG_PREEMPT to work again.  We were trashing
r20 by accident.

fails:

shmctl(shmid, IPC_STAT, &shmid_ds) 

The patch corrects the definition of the ipc_perm32 structure.

This one is similar to msgctl. We should be calling sys_shmctl with
struct shmid64_ds.

In the absence of this patch:

shmctl(shmid, IPC_SET, &shmid_ds)

will fail.

IA-32 programs executing:

msgctl(id, IPC_SET, &buf)

currently fail with EPERM due to this bug.

Patch by Rohit Seth, Fengua Yu, and Arun Sharma:

Please find attached a patch for kernel entry exit optimization. This is
based on 2.5.69 kernel.

The main items covered by this patch are:
1) Support for 16 bytes instructions as per SDM2.1 (CSD/SSD in pt_regs)
2) f10-f11 are added as additional scratch registers for kernel's use.
3) Re-arrange pt_regs to access less cache lines in system call. Reduce
scratch register saving/restoring in system call path.
4) A few instruction reorg in low-level code.

	came out wrong.

Some patches from hch@infradead.org cleaning up sn2 code a bit,
including the removal of some unnecessary files.

This patch moves the kernel text and data into region 5 (0xa00...) by using
a translation register to pin the entire area (i.e., no TLB faults).
The 1st-order goal is to be able to boot a kernel even when there is
no usable memory in the 64-128MB range.  It is also a step towards enabling
text-replication on NUMA.

This patch allows users to set the PMC to their default value, even
though the value might conflict with the type of monitoring
session. This is fine because default values ensure the monitor is not
active.

      callbacks so last_nsec_offset gets updated, too.

	so it handles not-present translations for region 5 (patch by John Marvin).

      changes by yours truly.

is INT_MAX and the value of size for n = INT_MAX is 268435456. So I don't think
there'll be an overflow.

Make it possible to plug in alternate time-offset sources, such as external
(e.g., chipset) timers or High-Performance Event Timer (HPET) etc. This
is needed on platforms where the cycle-counters on different CPUs may
drift apart from each other.
This patch contains the ia64-specific portion only.

	kernel if CONFIG_MD_RAID5 is declared.