- 14 Dec, 2023 10 commits
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Fabio Estevam authored
Per nxp,ptn5110.yaml, 'port' should be placed under 'connector'. Do as requested to fix the following dt-schema warning: imx8mn-evk.dtb: tcpc@50: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml#Signed-off-by:
Fabio Estevam <festevam@denx.de> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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Fabio Estevam authored
Per nxp,ptn5110.yaml, 'port' should be placed under 'connector'. Do as requested to fix the following dt-schema warning: imx8mm-evkb.dtb: tcpc@50: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml#Signed-off-by:
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Hugo Villeneuve authored
The Dimonoff gateway EVK board is based on a Variscite VAR-SOM-NANO, with a NXP MX8MN nano CPU and also based on a Symphony mx8mn EVK. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by:
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Alexander Stein authored
Device tree specification 0.4 defines an optional, but recommended 'chassis-type' property. Add it to TQMa8M* based board files. Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by:
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Adam Ford authored
The SoC is configured to operate in overdrive mode, so it is safe to include imx8mn-overdrive to run the GPU faster. Signed-off-by:
Adam Ford <aford173@gmail.com> Signed-off-by:
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Adam Ford authored
The i.MX8M Nano supports and overdrive mode if the SoC is given the proper voltage. Add imx8mn-overdrive.dtsi file which can be included by boards who support the voltage necessary to handle the faster clocks. This increases the GPU clocks from 400MHz to 600MHz. Signed-off-by:
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Adam Ford authored
The SoC runs at a high enough voltage to support overdrive mode, so include the imx8mm-overdrive.dtsi file to increase the VPU and GPU clocks to their overdrive speeds. Signed-off-by:
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Adam Ford authored
For boards who run their SoC at a higher voltage than nominal, the boards can run several clocks at an overdrive rate for better performance. Add an optional DTSI file which can be included by various boards to run in overdrive mode. This raises the GPU PLL to 1000MHz, and the VPU PLL to 700MHz while moving VPU_G1 and VPU_H1 to the SYS_PLL3_OUT which runs at 750MHz. Signed-off-by:
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Adam Ford authored
When the GPU nodes were added, the GPU_PLL_OUT was configured for 1000MHz, but this requires the SoC to run in overdrive mode which requires an elevated voltage operating point. Since this may run some boards out of spec, the default clock should be set to 800MHz for nominal operating mode. Boards that run at the higher voltage can update their clocks accordingly. Fixes: 4523be8e ("arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core") Signed-off-by:
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Fabio Estevam authored
fsl,micfil.yaml defines the clock-names in the following sequence: clock-names: items: - const: ipg_clk - const: ipg_clk_app - const: pll8k - const: pll11k - const: clkext3 minItems: 2 imx93.dtsi currently misses the 'pll11k' entry and jump to 'clkext3'. This leads to the following dt-schema warning: imx93-11x11-evk.dtb: micfil@44520000: clock-names:3: 'pll11k' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,micfil.yaml# Fix the warning by describing the clocks up to 'pll8k' as 'clkext3' is assigned to a dummy clock. Signed-off-by:
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- 13 Dec, 2023 3 commits
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Gregor Herburger authored
Add the different serdes configurations as overlays. Signed-off-by:
Gregor Herburger <gregor.herburger@ew.tq-group.com> Reviewed-by:
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Frank Li authored
Add I3C1 and I3C2. Signed-off-by:
Frank Li <Frank.Li@nxp.com> Signed-off-by:
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Fabio Estevam authored
Per qoriq-thermal.yaml, 'big-endian' is not a valid property. When the 'little-endian' property is absent, the default is big endian. Remove it to fix the following schema warning: tmu@1f00000: 'big-endian' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/thermal/qoriq-thermal.yaml#Signed-off-by:
Li Yang <leoyang.li@nxp.com> Signed-off-by:
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- 06 Dec, 2023 27 commits
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David Heidelberg authored
No functional changes. Adjust to comply with dt-schema requirements and make possible to validate values. Signed-off-by:
David Heidelberg <david@ixit.cz> Signed-off-by:
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Joao Paulo Goncalves authored
Add Toradex Verdin IMX8MP Mallow carrier board support. Mallow is a low-cost carrier board in the Verdin family with a small form factor and build for volume production making it ideal for industrial and embedded applications. https://www.toradex.com/products/carrier-board/mallow-carrier-boardSigned-off-by:
Joao Paulo Goncalves <joao.goncalves@toradex.com> Signed-off-by:
Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by:
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Joao Paulo Goncalves authored
Add Toradex Verdin IMX8MM Mallow carrier board support. Mallow is a low-cost carrier board in the Verdin family with a small form factor and build for volume production making it ideal for industrial and embedded applications. https://www.toradex.com/products/carrier-board/mallow-carrier-boardSigned-off-by:
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Fabio Estevam authored
As per Rob Herring's feedback: "The ethernet device should have a node name of 'ethernet'. The 'pcie' node name and 'device_type = "pci"' is for PCI buses/bridges only." Do it as suggested. Fixes: d61c5068729a ("arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes") Suggested-by:Rob Herring <robh@kernel.org> Signed-off-by:
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Adam Ford authored
Since commit 8208181f ("clk: imx: composite-8m: Add imx8m_divider_determine_rate") the lcdif controller has had the ability to set the lcdif_pixel rate which propagates up the tree and sets the video_pll1 rate automatically. By setting this value low, it will force the recalculation of video_pll1 to the lowest rate needed by lcdif instead of dividing a larger clock down to the desired clock speed. This has the advantage of being able to lower the video_pll1 rate from 594MHz to 148.5MHz when operating at 1080p. It can go even lower when operating at lower resolutions and refresh rates. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM Signed-off-by:
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Adam Ford authored
There are two clock-rate assignments for video_pll1, and the only one it should really have belongs inside the lcdif node, since it's the only consumer of this clock. Remove it from the clk node. Signed-off-by:
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Adam Ford authored
The device tree clock structure for the mipi_dsi is unnecessarily redundant. The default clock parent of IMX8MM_CLK_DSI_PHY_REF is already IMX8MM_CLK_24M, so there is no need to set the parent-child relationship between them. The default clock rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are already defined to be 266MHz and 24MHz respectively, so there is no need to define those clock rates. On i.MX8M[MNP] the samsung,pll-clock-frequency is not necessary, because the driver will read it from sclk_mipi which is also already set to 24MHz making it also redundant. Signed-off-by:
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by:
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Xu Yang authored
i.MX8DXL's ddr pmu has port/channel filter capabilities, but it still is compatible with "fsl,imx8-ddr-pmu". This will change the compatible. Signed-off-by:
Xu Yang <xu.yang_2@nxp.com> Signed-off-by:
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Alexander Stein authored
'dr_mode' is part of the USB DWC3 core, not the glue layer. Remove the property from glue layer. Fixes the dtbs_check warning: arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dtb: usb@32f10108: 'dr_mode' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#Signed-off-by:
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Fabio Estevam authored
The 'shared-interrupt' property is not documented nor used anywhere. Remove it. Signed-off-by:
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Fabio Estevam authored
The 'shared-interrupt' property is not documented nor used anywhere. Remove it. This fixes the following schema warning: imx93-11x11-evk.dtb: dma-controller@42000000: Unevaluated properties are not allowed ('shared-interrupt' was unexpected) from schema $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#Signed-off-by: -
Fabio Estevam authored
Per gpio-sbu-mux.yaml, the compatible entry is incomplete. The imx8qxp-mek board uses a CBDTU02043, so complete the gpio-sbu-mux compatible accordingly. This fixes the following schema warning: imx8qxp-mek.dtb: gpio-sbu-mux: compatible:0: 'gpio-sbu-mux' is not one of ['onnn,fsusb43l10x', 'pericom,pi3usb102'] from schema $id: http://devicetree.org/schemas/usb/gpio-sbu-mux.yaml#Signed-off-by:
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Fabio Estevam authored
The property 'phy-connection-type' can be used to describe the interface type between the Ethernet device and the Ethernet PHY device. However, snps,dwmac.yaml gives the following warning: imx8mp-debix-model-a.dtb: ethernet@30bf0000: 'phy-mode' is a required property from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml# To avoid the warning, switch to the more commonly used, 'phy-mode' property instead. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Fabio Estevam authored
Per i2c-mux-pca954x.yaml, the I2C subnodes should follow the 'i2c@' format. Change it to fix the following schema warning: imx8mm-nitrogen-r2.dtb: i2c-mux@70: Unevaluated properties are not allowed ('i2c3@0' was unexpected) from schema $id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#Signed-off-by: -
Fabio Estevam authored
Per snps,dwmac.yaml, the interrupt-names entries should be in the following order: "macirq", "eth_wake_irq"; Change it to fix the following schema warnings. imx8dxl-evk.dtb: ethernet@5b050000: interrupt-names:0: 'macirq' was expected from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml# imx8dxl-evk.dtb: ethernet@5b050000: interrupt-names:1: 'macirq' is not one of ['eth_wake_irq', 'eth_lpi'] from schema $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#Signed-off-by:
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Fabio Estevam authored
Per nxp,pcf8575.yaml, #gpio-cells should be 2. Change it to fix the following schema warning: imx8mm-emcon-avari.dtb: gpio@3a: #gpio-cells:0:0: 2 was expected from schema $id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#Signed-off-by:
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Fabio Estevam authored
Per fsl-lpuart.yaml, when the 'dmas' property is used 'dma-names' should also be present. Pass the lpuart 'dma-names' property to fix the following schema warnings: imx8dxl-evk.dtb: serial@5a060000: dma-names:0: 'rx' was expected from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# imx8dxl-evk.dtb: serial@5a060000: dma-names:1: 'tx' was expected from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml# imx8dxl-evk.dtb: serial@5a060000: Unevaluated properties are not allowed ('dma-names' was unexpected) from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#Signed-off-by:
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Oleksij Rempel authored
Add Skov i.MX8MP based climate controller. Signed-off-by:
Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by:
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Hugo Villeneuve authored
The following warning is shown when probing device: pca953x 1-0020: supply vcc not found, using dummy regulator Define a new fixed 3.3v regulator for carrier board peripherals, enabled by mosfet switch Q2 after the SOM_3V3 supply rises (no software control). Add this new regulator as vcc supply to the PCA9534 to silence the warning. Signed-off-by: -
Hugo Villeneuve authored
The RVE gateway board is based on a Variscite VAR-SOM-NANO, with a NXP MX8MN nano CPU. Signed-off-by:
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Kieran Bingham authored
Provide the 1.8 and 3.3 volt regulators that are utilised on the Debix SOM BMB-08 base board. Facilitate this by also supplying the pin control used to enable the regulators on the second MIPI CSI port. Reviewed-by:
Marco Felsch <m.felsch@pengutronix.de> Signed-off-by:
Kieran Bingham <kieran.bingham@ideasonboard.com> Signed-off-by:
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Andrejs Cainikovs authored
Newer variants of Ixora boards require a power-up delay when powering up the CAN transceiver of up to 1ms. Signed-off-by:
Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Signed-off-by:
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Hugo Villeneuve authored
When the EEPROM is probed, we have this warning: at24 0-0052: supply vcc not found, using dummy regulator Add fixed 3.3v regulator to silence the warning. Signed-off-by: -
Fabio Estevam authored
Several schema warnings are seen when running: make dtbs_check DT_SCHEMA_FILES=pci-bus.yaml Fix them. Signed-off-by:
Tim Harvey <tharvey@gateworks.com> Signed-off-by:
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Alexander Stein authored
Even if the 'dsp' node is disabled the memory intended to be used by the DSP is reserved. This limits the memory range suitable for CMA allocation. Thus disable the dsp_reserved node. DSP users need to enable it in parallel to the 'dsp' node. Signed-off-by:
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Adam Ford authored
The NPU is based on the Vivante GC8000 and its power-domain is controlled my pgc_mlmix. Since the power-domain uses some of these clocks, setup the clock parent and rates inside the power-domain, and add the NPU node. The data sheet states the CLK_ML_AHB should be 300MHz for nominal, but 800MHz clock will divide down to 266 instead. Boards which operate in over-drive mode should update the clocks on their boards accordingly. When the driver loads, the NPU numerates as: etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002 Signed-off-by:
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