- 18 Jan, 2020 1 commit
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
amd-drm-next-5.6-2020-01-17: amdgpu: - Fix 32 bit harder - Powerplay cleanups - VCN fixes for Arcturus - RAS fixes - eDP/DP fixes - SR-IOV fixes - Re-enable S/G display for PCO/RV2 - Free stolen memory after init on gmc10 - DF hashing optimizations for Arcturus - Properly handle runtime pm in sysfs and debugfs - Unify more GC programming between amdgpu and amdkfd - Golden settings updates for gfx10 - GDDR6 training fixes - Freesync fixes - DSC fixes - TMDS fixes - Renoir USB-C fixes - DC dml updates from hw team - Pollock support - Mutex init regresson fix amdkfd: - Unify more GC programming between amdgpu and amdkfd - Use KIQ to setup HIQ rather than using MMIO scheduler: - Documentation fixes - Improve job distribution with load sharing drm: - DP MST fix Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200117213625.4722-1-alexander.deucher@amd.com
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- 17 Jan, 2020 2 commits
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José Roberto de Souza authored
When a main MST port is disconnected drivers should call drm_dp_mst_topology_mgr_set_mst() disabling the MST manager, this function will set manager mst_primary to NULL and it will cause the crash bellow on the next atomic check when trying to access mst_primary->port. As there is no use in running checks over managers that are not active this patch will skip it. [ 305.616450] [drm:drm_dp_mst_atomic_check] [MST PORT:00000000cc2049e9] releases all VCPI slots [ 305.625085] [drm:drm_dp_mst_atomic_check] [MST PORT:00000000020ab43e] releases all VCPI slots [ 305.633729] [drm:drm_dp_mst_atomic_check] [MST MGR:00000000cdd467d4] mst state 00000000b67672eb VCPI avail=63 used=0 [ 305.644405] BUG: kernel NULL pointer dereference, address: 0000000000000030 [ 305.651448] #PF: supervisor read access in kernel mode [ 305.656640] #PF: error_code(0x0000) - not-present page [ 305.661807] PGD 0 P4D 0 [ 305.664396] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 305.668789] CPU: 3 PID: 183 Comm: kworker/3:2 Not tainted 5.5.0-rc6+ #1404 [ 305.675703] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3201.A00.1905140358 05/14/2019 [ 305.689425] Workqueue: events drm_dp_delayed_destroy_work [ 305.694874] RIP: 0010:drm_dp_mst_atomic_check+0x138/0x2c0 [ 305.700306] Code: 00 00 00 41 29 d9 41 89 d8 4c 89 fa 4c 89 f1 48 c7 c6 b0 b1 34 82 bf 10 00 00 00 45 31 ed e8 3f 99 02 00 4d 8b bf 80 04 00 00 <49> 8b 47 30 49 8d 5f 30 4c 8d 60 e8 48 39 c3 74 35 49 8b 7c 24 28 [ 305.719169] RSP: 0018:ffffc90001687b58 EFLAGS: 00010246 [ 305.724434] RAX: 0000000000000000 RBX: 000000000000003f RCX: 0000000000000000 [ 305.731611] RDX: 0000000000000000 RSI: ffff88849fba8cb8 RDI: 00000000ffffffff [ 305.738785] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000001 [ 305.745962] R10: ffffc900016879a0 R11: ffffc900016879a5 R12: 0000000000000000 [ 305.753139] R13: 0000000000000000 R14: ffff8884905c9bc0 R15: 0000000000000000 [ 305.760315] FS: 0000000000000000(0000) GS:ffff88849fb80000(0000) knlGS:0000000000000000 [ 305.768452] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 305.774263] CR2: 0000000000000030 CR3: 0000000005610006 CR4: 0000000000760ee0 [ 305.781441] PKRU: 55555554 [ 305.784228] Call Trace: [ 305.786739] intel_atomic_check+0xb2e/0x2560 [i915] [ 305.791678] ? printk+0x53/0x6a [ 305.794856] ? drm_atomic_check_only+0x3e/0x810 [ 305.799417] ? __drm_dbg+0x82/0x90 [ 305.802848] drm_atomic_check_only+0x56a/0x810 [ 305.807322] drm_atomic_commit+0xe/0x50 [ 305.811185] drm_client_modeset_commit_atomic+0x1e2/0x250 [ 305.816619] drm_client_modeset_commit_force+0x4d/0x180 [ 305.821921] drm_fb_helper_restore_fbdev_mode_unlocked+0x46/0xa0 [ 305.827963] drm_fb_helper_set_par+0x2b/0x40 [ 305.832265] drm_fb_helper_hotplug_event.part.0+0xb2/0xd0 [ 305.837755] drm_kms_helper_hotplug_event+0x21/0x30 [ 305.842694] process_one_work+0x25b/0x5b0 [ 305.846735] worker_thread+0x4b/0x3b0 [ 305.850439] kthread+0x100/0x140 [ 305.853690] ? process_one_work+0x5b0/0x5b0 [ 305.857901] ? kthread_park+0x80/0x80 [ 305.861588] ret_from_fork+0x24/0x50 [ 305.865202] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 btusb btrtl btbcm btintel bluetooth prime_numbers snd_hda_intel snd_intel_dspcfg snd_hda_codec e1000e snd_hwdep snd_hda_core thunderbolt mei_hdcp mei_me asix cdc_ether x86_pkg_temp_thermal r8152 mei coretemp usbnet snd_pcm mii crct10dif_pclmul ptp crc32_pclmul ecdh_generic ghash_clmulni_intel pps_core ecc i2c_i801 intel_lpss_pci [ 305.903096] CR2: 0000000000000030 [ 305.906431] ---[ end trace 70ee364eed801cb0 ]--- [ 305.940816] RIP: 0010:drm_dp_mst_atomic_check+0x138/0x2c0 [ 305.946261] Code: 00 00 00 41 29 d9 41 89 d8 4c 89 fa 4c 89 f1 48 c7 c6 b0 b1 34 82 bf 10 00 00 00 45 31 ed e8 3f 99 02 00 4d 8b bf 80 04 00 00 <49> 8b 47 30 49 8d 5f 30 4c 8d 60 e8 48 39 c3 74 35 49 8b 7c 24 28 [ 305.965125] RSP: 0018:ffffc90001687b58 EFLAGS: 00010246 [ 305.970382] RAX: 0000000000000000 RBX: 000000000000003f RCX: 0000000000000000 [ 305.977571] RDX: 0000000000000000 RSI: ffff88849fba8cb8 RDI: 00000000ffffffff [ 305.984747] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000001 [ 305.991921] R10: ffffc900016879a0 R11: ffffc900016879a5 R12: 0000000000000000 [ 305.999099] R13: 0000000000000000 R14: ffff8884905c9bc0 R15: 0000000000000000 [ 306.006271] FS: 0000000000000000(0000) GS:ffff88849fb80000(0000) knlGS:0000000000000000 [ 306.014407] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 306.020185] CR2: 0000000000000030 CR3: 000000048b3aa003 CR4: 0000000000760ee0 [ 306.027404] PKRU: 55555554 [ 306.030127] BUG: sleeping function called from invalid context at include/linux/percpu-rwsem.h:38 [ 306.039049] in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 183, name: kworker/3:2 [ 306.047272] INFO: lockdep is turned off. [ 306.051217] irq event stamp: 77505 [ 306.054647] hardirqs last enabled at (77505): [<ffffffff81a0c147>] _raw_spin_unlock_irqrestore+0x47/0x60 [ 306.064270] hardirqs last disabled at (77504): [<ffffffff81a0bedf>] _raw_spin_lock_irqsave+0xf/0x50 [ 306.073404] softirqs last enabled at (77402): [<ffffffff81e00389>] __do_softirq+0x389/0x47f [ 306.081885] softirqs last disabled at (77395): [<ffffffff810b83a9>] irq_exit+0xa9/0xc0 [ 306.089859] CPU: 3 PID: 183 Comm: kworker/3:2 Tainted: G D 5.5.0-rc6+ #1404 [ 306.098167] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3201.A00.1905140358 05/14/2019 [ 306.111882] Workqueue: events drm_dp_delayed_destroy_work [ 306.117314] Call Trace: [ 306.119780] dump_stack+0x71/0xa0 [ 306.123135] ___might_sleep.cold+0xf7/0x10b [ 306.127399] exit_signals+0x2b/0x360 [ 306.131014] do_exit+0xa7/0xc70 [ 306.134189] ? kthread+0x100/0x140 [ 306.137615] rewind_stack_do_exit+0x17/0x20 Fixes: cd82d82c ("drm/dp_mst: Add branch bandwidth validation to MST atomic check") Cc: Mikita Lipski <mikita.lipski@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Lyude Paul <lyude@redhat.com> Acked-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Pan, Xinhui authored
Initialize notifier_lock. Bug: https://gitlab.freedesktop.org/drm/amd/issues/1016Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
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- 16 Jan, 2020 37 commits
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Wenjing Liu authored
[why] DPG is used to generate both blank and test automation test pattern. When test automation is running the requested test pattern can be overriden by the blank or unblank call because it is using the same hardware. [how] When test pattern is requested, skip blank or unblank. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
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Paul Hsieh authored
[Why] Try to allocate MST payload but receive HPD short pulse with link loss casue driver allocate payload twice. It cause monitor can't light up successfully. [How] When driver receive HPD short pulse with link loss, we need to deallocate payload then allocate payload. Then we will not allocate payload twice with same sink. Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Jun Lei authored
[why] Need to fix DML portability issues to enable SW unit testing around DML [how] Move calcs into dc include folder since multiple components reference it Remove relative paths to external dependencies Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Tsai authored
[why] The rapid msleep operation causes the white line garbage when DAL check flip pending status in SetVidPnSourceVisibility. To execute this msleep will induce context switch, and longer delay could cause worse garbage situation. [how] To replace msleep with mdelay. Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
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Yongqiang Sun authored
Only need to do surface flip for video plane via dmcub. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Alvin Lee authored
[Why] Currently if seamless boot is enabled, we will skip double buffer enable for OTG_BLANK. However, we need the double buffer enable in order to block global sync signals when OTG becomes blanked (for PSR). Blocking global sync signals prevent pipe from requesting data. [How] Move tg_init before seamless boot check. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] dpcd cap mismatch in 2200 vs base [How] Add monitor patch which using based caps to overwrite 2200 Signed-off-by:
Lewis Huang <Lewis.Huang@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] Currently we wait for test pattern after each pipe is programmed. For ODM combined scenario it will cause test pattern is shown on only half screen for 1 frame. This is not desirable. [how] No wait between odm pipe programming, only wait after all pipes are programmed. Signed-off-by:
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Anthony Koo authored
[Why] With different refresh rate panels, the PSR entry/exit time is different since it is dependent on 2 frame entry time today [How] Make static screen num frame entry time to be calculated such that entry time is within 30 ms instead of fixed num frames. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Lewis Huang authored
[Why] DMCU need to wait a vblank to handle psr enter command. When psr exit coming before vblank, the psr exit command will be skip because current psr state is disable. [How] remove psr state condition when psr exit case Signed-off-by:
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Josip Pavic authored
[Why] IRAM definition needed for versions of DMCU containing ABM 2.4 [How] Pass ABM 2.3 IRAM definition, which is compatible with ABM 2.4, to DMCU when ABM 2.4 FW is detected Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Chris Park authored
Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
Jordan Lazare <Jordan.Lazare@amd.com> Acked-by:
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Sung Lee authored
[Why] DML Initialization was previously done on dcn21_resource initialization. This meant that DML soc struct was populated with hardcoded values. [How] Move DML initialization to after updating bounding box, to use clock table values from SMU. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
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George Shen authored
[Why] PHY will sometimes be in bad state on hotplugging display from USB-C dongle. [How] Add additional calls to disable and then enable PHY before link training starts during verify_link_cap. Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] The DMUB PSR command IDs do not have the correct values. [How] Fix the command IDs and cleanup the formatting. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Yongqiang Sun authored
Rework surface programming for RN to separate preparing parameters and register programming. Signed-off-by:
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Noah Abradjian authored
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data. [How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ. Signed-off-by:
Noah Abradjian <noah.abradjian@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Moving PSR from DMCU to DMCUB. [How] Cleanup psr spec files and add PSR hw programming files. No functionality is included in this change. Signed-off-by:
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Yongqiang Sun authored
Programming surface flip addresses via dmcub uC for optimizing the data flush. Signed-off-by:
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Noah Abradjian authored
[Why] When rapidly adjusting color temperature, screen tearing was observed. This was due to overwritten values in gamut remap registers. This issue was solved for OCSC and ICSC by alternating between "A" and "B" registers to double buffer the writes. [How] Create new set_gamut_remap and program_gamut_remap for dcn20. Alternate which registers are written to by switching modes each time. Also fixes ICSC mode reg read to use proper data offset. Signed-off-by:
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Wyatt Wood authored
[Why] Moving PSR from DMCU to DMCUB. [How] Add driverside PSR changes required to send inbox messages to fw. These changes are non-functional until the psr structure allocation is uncommented. Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Noah Abradjian authored
[Why] When rapidly adjusting video brightness, screen tearing was observed. This was due to overwritten values in ICSC registers. In dcn10, this issue had been fixed by implementing double buffering via alternating ICSC modes. However, the second register set used in dcn1 doesn't exist in dcn2. [How] Create new program_input_csc for dcn20. Use ICSC_B registers instead of COMA registers as second set. Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Dmytro Laktyushkin authored
Add more fields to support upcoming dml versions Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Joseph Gravenor authored
[Why] Don't want to start HW discovery unless we have lost power, as doing rediscovery otherwise is both unnecessary and time consuming. Before this change it takes 40 seconds to go in to suspend, after it takes 27 seconds [How] Accelerated mode gets cleared if we lose power. Only do detection if this register is cleared Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Wenjing Liu authored
Test pattern should be applied to hardware when exiting set test pattern function. Signed-off-by:
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Michael Strauss authored
[WHY] 48mhz turn off feature does not work on HDMI and DVI, but the feauture was only blocked on HDMI, this change will apply the same wa on DVI [HOW] Apply workaround for all TMDS signal types (HDMI, DVI single/dual link) Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Alvin Lee authored
[Why] If dummy pstate latency is 0 we should report the actual pstate support, and not that pstate is always supported. [How] Don't always program pstate support true Signed-off-by:
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abdoulaye berthe authored
Make sure that lttpr_caps has the mode set to repeater. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
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Noah Abradjian authored
[Why] When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed. This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by implementing double buffering by alternating OCSC modes. [How] Alternate which OCSC registers are used by switching modes each time. This double buffers the CSC writes. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We need to ensure that the DMUIF in MMHUBBUB is also in reset so we aren't generating requests while the DMCUB is in reset. [How] Set DMUIF_SOFT_RESET=1 on reset and DMUIF_SOFT_RESET=0 on reset release. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] The inst firmware isn't necessarily fully flushed to framebuffer memory and the DMCUB can hang due to invalid inst being parsed. [How] Like the fix to flush ringbuffer commands before updating the inbox write pointer we need to read back inst memory before writing the CW0 registers. Add a helper to read 64-byte chunks to avoid a large temporary buffer. Read the remaining leftover bytes if the inst_fb isn't fully aligned. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] There's a data race that can occur between when we update the inbox write pointer vs when the memory for the command actually gets flushed from the map to the framebuffer. DMCUB can read stale or partially invalid data when this race occurs. [How] Before updating the write pointer we can read back all pending commands to ensure that we stall for the writes to be flushed to framebuffer. We don't need to worry about choosing HDP vs VM flush with this mechanism. Drop the dmub_srv_cmd_submit() while we're updating this to work correctly since nothing was actually using this API and the caller should be explicit about the API flow here - by doing this on execute we can give some extra time for the flush to finish while preparing other commands. We should try to avoid writing single commands because of this overhead. Signed-off-by:
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Martin Leung authored
[why] While doing seamless boot I made some changes to dcn2 hubbub functions, missed a link [how] link hubbub1 func to hubbub2 usage. It has already been successfully linked in dcn1 and 3. Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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