- 31 Mar, 2021 17 commits
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Kishon Vijay Abraham I authored
No functional change. Since the reset controls obtained in Torrent is exclusively used by the Torrent device, use exclusive reset control request API calls. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by:
Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210330110138.24356-5-kishon@ti.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Kishon Vijay Abraham I authored
Do not configure torrent SERDES if it's already configured. Signed-off-by:
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Kishon Vijay Abraham I authored
No functional change intended. Group reset APIs and clock APIs in preparation for adding support to skip configuration if the SERDES is already configured by bootloader. Signed-off-by:
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Faiz Abbas authored
Serdes lanes might be shared between multiple cores in some usecases and its not possible to lock PLLs for both the lanes independently by the two cores. This requires a bootloader to configure both the lanes at early boot time. To handle this case, skip all configuration if any of the lanes has already been enabled. Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
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Kishon Vijay Abraham I authored
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by:
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Kishon Vijay Abraham I authored
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by:
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Kishon Vijay Abraham I authored
Add #clock-cells binding to model Sierra as clock provider and include clock IDs for PLL_CMNLC and PLL_CMNLC1. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319124128.13308-12-kishon@ti.comSigned-off-by:
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Kishon Vijay Abraham I authored
commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY") enabled the clock in probe and failed to disable in remove callback. Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by:
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Kishon Vijay Abraham I authored
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by:
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Kishon Vijay Abraham I authored
No functional change. In order to have a single header file for all Cadence SERDES move phy-cadence-torrent.h to phy-cadence.h. This is in preparation for adding Cadence Sierra SERDES specific macros. Signed-off-by:
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Kishon Vijay Abraham I authored
No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.comSigned-off-by:
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Kishon Vijay Abraham I authored
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by:
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Kishon Vijay Abraham I authored
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by:
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Kishon Vijay Abraham I authored
"serdes" node (child node of WIZ) can have sub-nodes for representing links or it can have sub-nodes for representing the various clocks within the serdes. Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy" or "link" subnode. Ideally all PHY dt nodes should have node name as "phy", however existing devicetree used "link" as subnode. So in order to maintain old DT compatibility get PHY properties for "phy" or "link" subnode. Signed-off-by:
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Kishon Vijay Abraham I authored
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by:
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Kishon Vijay Abraham I authored
Invoke wiz_init() before configuring anything else in Sierra/Torrent (invoked as part of of_platform_device_create()). wiz_init() resets the SERDES device and any configuration done in the probe() of Sierra/Torrent will be lost. In order to prevent SERDES configuration from getting reset, invoke wiz_init() immediately before invoking of_platform_device_create(). Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by:
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Kishon Vijay Abraham I authored
Commit 44d30d62 ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d62 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by:
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- 30 Mar, 2021 19 commits
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Kuogee Hsieh authored
Add hbr3_hbr2 voltage and premphasis swing table to support HBR3 link rate. Signed-off-by:
Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615914761-12300-1-git-send-email-khsieh@codeaurora.org Fixes: 52e013d0 ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Signed-off-by:
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Wei Yongjun authored
Fix the return value check typo which testing the wrong variable in ingenic_usb_phy_probe(). Fixes: 31de313d ("PHY: Ingenic: Add USB PHY driver using generic PHY framework.") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Acked-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210305034933.3240914-1-weiyongjun1@huawei.comSigned-off-by:
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Wei Yongjun authored
Fix the return value check which testing the wrong variable in mt7621_pci_phy_probe(). Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by:
Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.comSigned-off-by:
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Geert Uytterhoeven authored
Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ARMADA375_USBCLUSTER_PHY to MACH_ARMADA_375, and ask the user in case of compile-testing. Fixes: eee47538 ("phy: add support for USB cluster on the Armada 375 SoC") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210208150252.424706-1-geert+renesas@glider.beSigned-off-by:
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Yang Li authored
In one of the error paths of the for_each_child_of_node() loop in of_property_read_u32, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/phy/ti/phy-j721e-wiz.c:786:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 795. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1614244674-66556-1-git-send-email-yang.lee@linux.alibaba.comSigned-off-by:
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Sergio Paracuellos authored
When this was rewriten to get mainlined and start to use 'linux/bitfield.h' headers, XTAL_MASK was wrong. It must mask three bits but only two were used. Hence properly fix it to make things work. Fixes: d87da323 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Signed-off-by:
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Swapnil Jakhade authored
Update PCIe + USB register sequences for correct PLL1 clock configuration. Also, update sequences for other USB configurations with dependent changes. Signed-off-by:
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Kishon Vijay Abraham I authored
Update SGMII/QSGMII configuration specific to TI. Signed-off-by:
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Kishon Vijay Abraham I authored
Configure MAC clock dividers required for QSGMII to be functional. Signed-off-by:
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Swapnil Jakhade authored
For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by:
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Kishon Vijay Abraham I authored
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by:
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Kishon Vijay Abraham I authored
cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Signed-off-by:
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Kishon Vijay Abraham I authored
commit 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.orgSigned-off-by:
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Kishon Vijay Abraham I authored
The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by:
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Kishon Vijay Abraham I authored
commit 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by:
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Kishon Vijay Abraham I authored
Both "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" are static data that is common for all wiz instances. Including "struct regmap_field" for each of the wiz instances can yield undesirable results. Move "struct regmap_field" out of "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" and make them point to constant data. So far no issues are observed since both these structures are not accessed outside the probe. Signed-off-by:
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Konstantin Porotchkin authored
Add DTS binding for Marvell CP110 UTMI PHY Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Reviewed-by:
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Konstantin Porotchkin authored
The new file name is marvell,armada-3700-utmi-phy.yaml Signed-off-by:
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Konstantin Porotchkin authored
Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by:
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- 25 Mar, 2021 4 commits
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Zhang Yunkai authored
'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by:
Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cnSigned-off-by:
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Bhaskar Chowdhury authored
s/subsytem/subsystem/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Link: https://lore.kernel.org/r/20210320204055.26107-1-unixbhaskar@gmail.comSigned-off-by:
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Sandeep Maheswaram authored
Add the compatible string for sc7280 SoC from Qualcomm Signed-off-by:
Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Reviewed-by:
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Chunfeng Yun authored
The phy may be named as pcie-phy when the T-PHY only supports PCIe mode, it's also the similar case for SATA, named as sata-phy. Reviewed-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20210316092232.9806-4-chunfeng.yun@mediatek.comSigned-off-by:
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