- 23 May, 2023 10 commits
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Konrad Dybcio authored
The board hosts a whole lot of fixed regulators. Describe them. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-and-Tested-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230515-topic-rb2-bits-v1-1-a52d154a639d@linaro.org
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Krzysztof Kozlowski authored
Add missing parts of USB stack to enable USB OTG mode. The QRD8550 comes with one USB Type-C port. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Krzysztof Kozlowski authored
Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected, thus skip pcie_1_phy_aux_clk input clock to GCC. Signed-off-by:
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Neil Armstrong authored
With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the Type-C connector, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Signed-off-by:
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Neil Armstrong authored
With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the Type-C connector, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Reviewed-by:
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Neil Armstrong authored
Add the USB3+DP Combo QMP PHY port subnodes in the SM8450 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by:
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Neil Armstrong authored
Add the USB3+DP Combo QMP PHY port subnodes in the SM8350 SoC DTSI to avoid duplication in the devices DTs. Signed-off-by:
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Bjorn Andersson authored
The CRD has Micro SD slot, introduce the necessary DeviceTree nodes for enabling this. Signed-off-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by:
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Bjorn Andersson authored
Following the CRD, connect the two QMP phys inbetween the USB Type-C connectors and the DisplayPort controller, to handle orientation switching. Tested-by:
Abel Vesa <abel.vesa@linaro.org> Tested-by:
Steev Klimaszewski <steev@kali.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450 Tested-by: Johan Hovold <johan+linaro@kernel.org> # X13s Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Bjorn Andersson authored
With support for the QMP combo phy to react to USB Type-C switch events, introduce it as the next hop for the SuperSpeed lanes of the two USB Type-C connectors, and connect the output of the DisplayPort controller to the QMP combo phy. This allows the TCPM to perform orientation switching of both USB and DisplayPort signals. Tested-by:
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- 18 May, 2023 7 commits
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Devi Priya authored
Drop unused bias_pll_ubi_nc_clk input to the clock controller. Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
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Devi Priya authored
Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR registers lie in the second 4kB region. Also, add target CPU encoding. Fixes: 97cb36ff ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support") Signed-off-by:
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André Apitzsch authored
l8910 uses OCP8110 flash LED driver. Add it to the device tree. Tested-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
André Apitzsch <git@apitzsch.eu> Signed-off-by:
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Konrad Dybcio authored
We need more granularity for things like the GPU. Add the missing levels. This unfortunately requires some re-indexing, resulting in an ugly diff. Rename the nodes to prevent that in the future. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Konrad Dybcio authored
After adding the missing levels with a nice, easy-to-read diff, reformat the defines to make them nice to look at.. Acked-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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Konrad Dybcio authored
There are a lot of RPMh levels that we haven't included yet.. some sadly turned out to be necessary, add them! Acked-by:
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Bartosz Golaszewski authored
The UFS controller is cache coherent, so mark it as such in the dtsi. Fixes: be543efe ("arm64: dts: qcom: sa8775p: add UFS nodes") Signed-off-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Suggested-by:
Manivannan Sadhasivam <mani@kernel.org> Reviewed-by:
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- 15 May, 2023 20 commits
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Krzysztof Kozlowski authored
GIC child node is supposed to be named msi-controller: sa8295p-adp.dtb: interrupt-controller@17a00000: gic-its@17a40000: False schema does not allow Reviewed-by:
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Krzysztof Kozlowski authored
Qualcomm PCI express root complex does not use snps,dw-pcie fallback: ['qcom,pcie-sm8150', 'snps,dw-pcie'] is too long Reviewed-by:
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Krzysztof Kozlowski authored
Since commit 6c84bbd1 ("dt-bindings: arm-smmu: Add generic qcom,smmu-500 bindings") the SMMU is supposed to use qcom,smmu-500 compatible fallback. Signed-off-by:
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Krzysztof Kozlowski authored
Drop incorrect and unused serial properties - address/size-cells and reg-names: sa8155p-adp.dtb: geniqup@ac0000: serial@a84000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'reg-names' were unexpected) Reviewed-by: -
Bartosz Golaszewski authored
Enable the always-on subsystem controller on SA8775P platforms for use by upcoming support for other peripherals. Signed-off-by:
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Shazad Hussain authored
Enable usb0, usb1 and usb2 nodes and their respective phy's. Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> Reviewed-by:
Adrien Thierry <athierry@redhat.com> Signed-off-by:
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Shazad Hussain authored
Add nodes for the USB and it's PHY on sa8775p platform. Signed-off-by:
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Bartosz Golaszewski authored
Now that the hypervisor issue is fixed, we can add the watchdog node for sa8775p platforms. Signed-off-by:
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Parikshit Pareek authored
Introduce sdam_0 node, which is to be used via nvmem for power on reasons during reboot. Add supported PoN reaons supported via sdam_0 node. Signed-off-by:
Parikshit Pareek <quic_ppareek@quicinc.com> Signed-off-by:
Eric Chanudet <echanude@redhat.com> Reviewed-by:
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Parikshit Pareek authored
On this PMIC, the PON peripheral does not provide passing reboot modes over HLOS. They must be passed over SDAM. Remove the reboot-mode properties as we'll provide a proper SDAM node in a later commit. Fixes: d2d9a592 ("arm64: dts: qcom: sa8775p: add the Power On device node") Signed-off-by:
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Bartosz Golaszewski authored
Add the Adreno GPU IOMMU for sa8775p-based platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add the GPUCC node for sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add the PCIe SMMU node for sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Enable the UFS and its PHY on sa8775p-ride. Signed-off-by:
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Bartosz Golaszewski authored
Add nodes for the UFS and its PHY on sa8775p platforms. Signed-off-by:
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Bartosz Golaszewski authored
Add the PMU node for sa8775p platforms. Signed-off-by:
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Dang Huynh authored
The F(x)tec Pro1X is a mobile phone released by FX Technologies Ltd in 2022. The phone is exactly the same as the Pro1 released in 2019 with some changes: - MSM8998 -> SM6115 - Camera button is no longer multistate - Only one 48MP back camera - A new keyboard layout picked by the community. This commit has the following features working: - Display (using simplefb) - UFS - Power and volume buttons - Pinctrl - RPM Regulators - USB (Device Mode) To get a successful boot run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/\ sm6115-fxtec-pro1x.dtb > .Image.gz-dtb mkbootimg --kernel .Image.gz-dtb \ --ramdisk initrd.img \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --second_offset 0xf00000 \ --tags_offset 0x100 \ --pagesize 4096 \ --cmdline "CMDLINE HERE" \ -o qx1050-boot.img fastboot flash boot qx1050-boot.img fastboot erase dtbo fastboot reboot Signed-off-by:
Dang Huynh <danct12@riseup.net> Reviewed-by:
Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by:
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Dang Huynh authored
Document F(x)tec Pro1X as a SM6115 device. Signed-off-by:
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Andrew Halaney authored
Enable both the MACs found on the board. ethernet0 and ethernet1 both ultimately go to a series of on board switches which aren't managed by this processor. ethernet0 is connected to a Marvell 88EA1512 phy via RGMII. That goes to the series of switches via SGMII on the "media" side of the phy. RGMII_SGMII mode is enabled via devicetree register descriptions. The switch on the "media" side has auto-negotiation disabled, so configuration from userspace similar to: ethtool -s eth0 autoneg off speed 1000 duplex full is necessary to get traffic flowing on that interface. ethernet1 is in a mac2mac/fixed-link configuration going to the same series of switches directly via RGMII. Tested-by:Brian Masney <bmasney@redhat.com> Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Reviewed-by:
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Andrew Halaney authored
This platform has 2 MACs integrated in it, go ahead and describe them. Reviewed-by:
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- 11 May, 2023 2 commits
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Poovendhan Selvaraj authored
Add the required nodes to support SMEM Signed-off-by:
Poovendhan Selvaraj <quic_poovendh@quicinc.com> Signed-off-by:
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Poovendhan Selvaraj authored
Enable the support for download mode to collect the crashdumps if system crashes, to debug crashes extensively. Signed-off-by:
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- 07 May, 2023 1 commit
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Linus Torvalds authored
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