- 03 Mar, 2021 4 commits
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Kevin Wang authored
add SECUREDISPLAY TA firmware info in amdgpu_fimrware_info() Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Kevin Wang authored
refine PSP TA firmware info print in amdgpu_firmware_info(). Signed-off-by:
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Xiaojian Du authored
This patch is to correct the name of one function for vangogh. This function is used to print the clock levels of all kinds of IP components. Signed-off-by:
Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c:298:33-38: WARNING: conversion to bool not needed here. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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- 02 Mar, 2021 23 commits
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Chen Li authored
The number of chunks/chunks_array may be passed in by userspace and can be large. It has been observed to cause kcalloc failures from trinity fuzzy test: WARNING: CPU: 0 PID: 5487 at mm/page_alloc.c:4385 __alloc_pages_nodemask+0x2d8/0x14d0 Obviously, the required order in this case is larger than MAX_ORDER. So, just use kvmalloc instead. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Chen Li <chenli@uniontech.com> Signed-off-by:
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Arnd Bergmann authored
clang points out that the new logic uses an always-uninitialized array index: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9810:38: warning: variable 'i' is uninitialized when used here [-Wuninitialized] timing = &edid->detailed_timings[i]; ^ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9720:7: note: initialize the variable 'i' to silence this warning My best guess is that the index should have been returned by the parse_hdmi_amd_vsdb() function that walks an array here, so do that. Fixes: f9b4f20c ("drm/amd/display: Add Freesync HDMI support to DM") Reviewed-by:Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Colin Ian King authored
Currently if stream->signal is neither SIGNAL_TYPE_DISPLAY_PORT_MST or SIGNAL_TYPE_DISPLAY_PORT then variable ret is uninitialized and this is checked for > 0 at the end of the function. Ret should be initialized, I believe setting it to zero is a correct default. Addresses-Coverity: ("Uninitialized scalar variable") Fixes: bd0c064c ("drm/amd/display: Add return code instead of boolean for future use") Reviewed-by:Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
It works fine and was only disabled because primary GPUs don't enter runpm if there is a console bound to the fbdev due to the kmap. This will at least allow runpm on secondary cards. Reviewed-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com> Signed-off-by:
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Alex Deucher authored
The S0ix check only makes sense if the AMD PMC driver is present. We need to use the legacy S3 pathes when the PMC driver is not present. Reviewed-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Xiaogang Chen authored
amdgpu DM handles INTERRUPT_LOW_IRQ_CONTEXT interrupt(hpd, hpd_rx) by using work queue and uses single work_struct. If new interrupt is recevied before the previous handler finished, new interrupts(same type) will be discarded and driver just sends "amdgpu_dm_irq_schedule_work FAILED" message out. If some important hpd, hpd_rx related interrupts are missed by driver the hot (un)plug devices may cause system hang or instability, such as issues with system resume from S3 sleep with mst device connected. This patch dynamically allocates new amdgpu_dm_irq_handler_data for new interrupts if previous INTERRUPT_LOW_IRQ_CONTEXT interrupt work has not been handled. So the new interrupt works can be queued to the same workqueue_struct, instead of discard the new interrupts. All allocated amdgpu_dm_irq_handler_data are put into a single linked list and will be reused after. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Vladimir Stempen authored
[why] Synchronization displays with different timings feature uses reminder of 64 bit division (modulus operator) , which is not supported by 32 bit platforms [how] Use div64 API for 64 bit modulus Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Tested-by: Bindu Ramamurthy<bindu.r@amd.com> Signed-off-by:
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Vladimir Stempen authored
[why] Synchronization displays with different timings feature uses division operator for 64 bit division, which is not supported by 32 bit platforms [how] Use div64 API for 64 bit division Signed-off-by:
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Jonathan Kim authored
Request to stop DF performance counters is missing the actual write to the controller register. Reported-by:
Chris Freehill <chris.freehill@amd.com> Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Acked-by:
Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Signed-off-by:
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Dillon Varone authored
[Why?] HSplit should not affect DSC slice count. Can cause improper timings to be applied for certain modes. [How?] No longer change DSC Slice count based on HSplit. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Hugo Hu authored
[Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Tested-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Aric Cyr authored
DC version 3.2.125 brings improvements in multiple areas. In summary, we highlight: - DSC fixes - Enable ASSR - Firmware relase 0.0.54 - eDP interface refactor for multiple eDP Tested-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
Tested-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Yongqiang Sun authored
[Why & How] DMUB FW send trace event via outbox0 interrupt. Driver will handle it. Tested-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] GPINT timeout is causing PSR_STATE_0 to be returned when it shouldn't. We must guarantee that PSR is fully disabled before doing hw programming on driver-side. [How] Return invalid state if GPINT command times out. Let existing retry logic send the GPINT until successful. Tested-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Jake Wang authored
[Why & How] Some existing DC interfaces are optimized to return a single eDP link/stream. Refactored those DC interfaces to support multiple eDP. Tested-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Eryk Brol authored
[Why] Useful for testing when setting a max bpc value higher than the default is required [How] Allow for reading/writing of the max_requested_bpc property of the connector Tested-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
Mikita Lipski <Mikita.Lipski@amd.com> Acked-by:
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Max.Tseng authored
[why] Add flag to build infopacket in SDP v1.3 format Tested-by:
Max.Tseng <Max.Tseng@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why] Currently the creation of link encoder objects is tightly coupled to the creation of link objects. Decoupling link encoder object creation is a preliminary step in the process of allowing link encoders to be dynamically assigned to links. [How] Add "minimal" link encoder objects which are not associated with any link until required. Tested-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [HOW] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) As the driver holds dal and dc locks while waiting for CV, the outbox1 ISR is registered with noMutexWait set to true, which allows ISR to run and signal CV. This sets a constraint on ISR to not modify variables such as dc, dmub, etc. 4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable outbox1 mailbox. 5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE. Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(), dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr(). 6) Added functions dc_stat_get_dmub_notification() and dmub_srv_stat_get_notification() to retrieve Outbox1 message. 7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX transaction. A workaround is added in dce_aux_transfer_dmub_raw() to open in DDC in AUX mode for every AUX transaction. 8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable DMUB AUX. This debug option is checked dce_aux_transfer_with_retries() to select the method to process AUX transactions. Tested-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by:
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Evan Quan authored
By using the information provided by PMFW when available. V2: put those structures shared around SMU V11 ASICs in smu_v11_0.h Signed-off-by: -
Evan Quan authored
New changes were involved for the SmuMetrics structure. Signed-off-by:
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Kevin Wang authored
miss RAP TA in loop. (when i == 4) Fix: drm/amdgpu: add RAP TA version print in amdgpu_firmware_info Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Signed-off-by:
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- 26 Feb, 2021 13 commits
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c:273:16-21: WARNING: conversion to bool not needed here. Reported-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c:924:47-52: WARNING: conversion to bool not needed here. Reported-by:
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Dennis Li authored
If the number of badpage records exceed the threshold, driver has updated both epprom header and control->tbl_hdr.header before gpu reset, therefore GPU recovery thread no need to read epprom header directly. v2: merge amdgpu_ras_check_err_threshold into amdgpu_ras_eeprom_check_err_threshold Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
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Shirish S authored
report -ENOTSUPP instead of -EINVAL, so that if userspace fails to read sensor data can figure it out the failure correctly. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Evan Quan authored
Arcturus has a different register address from other SMU V11 ASICs. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Kevin Wang authored
add RAP TA version print in amdgpu_firmware_info. Signed-off-by:
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Jiapeng Chong authored
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp_cm.c:243:67-72: WARNING: conversion to bool not needed here. Reported-by:
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Yang Li authored
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1589:0-23: WARNING: fops_ib_preempt should be defined with DEFINE_DEBUGFS_ATTRIBUTE ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1592:0-23: WARNING: fops_sclk_set should be defined with DEFINE_DEBUGFS_ATTRIBUTE Reported-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Per discussions with PMFW team, the driver only needs to notify the PMFW when the RLC is disabled. The RLC FW will notify the PMFW directly when it's enabled. Acked-by:
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Alex Deucher authored
Making them an error confuses users and the errors are harmless as not all asics support all profiles. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1488Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Alex Deucher authored
And just use the ioctl index. They are the same. Reviewed-by:
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Alex Deucher authored
So mesa can check when to query the kernel vs use hardcoded codec bandwidth data. Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Alex Deucher authored
We currently hardcode these in mesa, but querying them from the kernel makes more sense since there may be board specific limitations that the kernel driver is better suited to determining. Userpace patches that use this interface: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps v2: reorder the codecs to better align with mesa v3: add max_pixels_per_frame to handle the portrait case, squash in memory leak fix v4: drop extra break Reviewed-by:
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