- 05 Dec, 2023 18 commits
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Hangbin Liu authored
The current bridge kernel doc is too old. It only pointed to the linuxfoundation wiki page which lacks of the new features. Here let's start the new bridge document and put all the bridge info so new developers and users could catch up the last bridge status soon. In this patch, Convert the doc to rst format. Add bridge brief introduction, FAQ and contact info. Reviewed-by:
Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by:
Hangbin Liu <liuhangbin@gmail.com> Acked-by:
Nikolay Aleksandrov <razor@blackwall.org> Signed-off-by:
Paolo Abeni <pabeni@redhat.com>
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Jakub Kicinski authored
Rohan G Thomas says: ==================== net: stmmac: EST implementation This patchset extends EST interrupt handling support to DWXGMAC IP followed by refactoring of EST implementation. Added a separate module for EST and moved all EST related functions to the new module. Also added support for EST cycle-time-extension. ==================== Link: https://lore.kernel.org/r/20231201055252.1302-1-rohan.g.thomas@intel.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Rohan G Thomas authored
Add support for cycle-time-extension. TER GCL-register needs to be updated with the cycle-time-extension. Width of TER register is EST time interval width + 7 bits. Signed-off-by:
Rohan G Thomas <rohan.g.thomas@intel.com> Reviewed-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231201055252.1302-4-rohan.g.thomas@intel.comSigned-off-by:
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Rohan G Thomas authored
Refactor EST implementation by moving common code for DWMAC4 and DWXGMAC IPs into a separate EST module. EST implementation for DWMAC4 and DWXGMAC differs only for CSR base address, PTOV field offset width, and PTOV clock multiplier value. Thanks, Serge Semin and Jakub Kicinski for the suggestions on refactoring EST implementation into a separate EST module. Signed-off-by:
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Rohan G Thomas authored
Enabled the following EST related interrupts: 1) Constant Gate Control Error (CGCE) 2) Head-of-Line Blocking due to Scheduling (HLBS) 3) Head-of-Line Blocking due to Frame Size (HLBF) 4) Base Time Register error (BTRE) 5) Switch to S/W owned list Complete (SWLC) Also, add EST errors into the ethtool statistic. The commit e49aa315 ("net: stmmac: EST interrupts handling and error reporting") and commit 9f298959 ("net: stmmac: Add EST errors into ethtool statistic") add EST interrupts handling and error reporting support to DWMAC4 core. This patch enables the same support for XGMAC. Signed-off-by:
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Ravi Gunasekaran authored
The errata i2329 affects all the currently available silicon revisions of AM62x, AM64x, AM65x, J7200, J721E and J721S2. So remove the revision string from the SoC list. The silicon revisions affected by the errata i2329 can be found under the MDIO module in the "Advisories by Modules" section of each SoC errata document listed below AM62x: https://www.ti.com/lit/er/sprz487c/sprz487c.pdf AM64X: https://www.ti.com/lit/er/sprz457g/sprz457g.pdf AM65X: https://www.ti.com/lit/er/sprz452i/sprz452i.pdf J7200: https://www.ti.com/lit/er/sprz491d/sprz491d.pdf J721E: https://www.ti.com/lit/er/sprz455d/sprz455d.pdf J721S2: https://www.ti.com/lit/er/sprz530b/sprz530b.pdfSigned-off-by:
Ravi Gunasekaran <r-gunasekaran@ti.com> Reviewed-by:
Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20231201132033.29576-1-r-gunasekaran@ti.comSigned-off-by:
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Jakub Kicinski authored
Amritha Nambiar says: ==================== Introduce queue and NAPI support in netdev-genl (Was: Introduce NAPI queues support) Add the capability to export the following via netdev-genl interface: - queue information supported by the device - NAPI information supported by the device Introduce support for associating queue and NAPI instance. Extend the netdev_genl generic netlink family for netdev with queue and NAPI data. The queue parameters exposed are: - queue index - queue type - ifindex - NAPI id associated with the queue Additional rx and tx queue parameters can be exposed in follow up patches by stashing them in netdev queue structures. XDP queue type can also be supported in future. The NAPI fields exposed are: - NAPI id - NAPI device ifindex - Interrupt number associated with the NAPI instance - PID for the NAPI thread This series only supports 'get' ability for retrieving certain queue and NAPI attributes. The 'set' ability for configuring queue and associated NAPI instance via netdev-genl will be submitted as a separate patch series. Previous discussion at: https://lore.kernel.org/netdev/c8476530638a5f4381d64db0e024ed49c2db3b02.camel@gmail.com/T/#m00999652a8b4731fbdb7bf698d2e3666c65a60e7 $ ./cli.py --spec netdev.yaml --do queue-get --json='{"ifindex": 12, "id": 0, "type": 0}' {'id': 0, 'ifindex': 12, 'napi-id': 593, 'type': 'rx'} $ ./cli.py --spec netdev.yaml --do queue-get --json='{"ifindex": 12, "id": 0, "type": 1}' {'id': 0, 'ifindex': 12, 'napi-id': 593, 'type': 'tx'} $ ./cli.py --spec netdev.yaml --dump queue-get --json='{"ifindex": 12}' [{'id': 0, 'ifindex': 12, 'napi-id': 593, 'type': 'rx'}, {'id': 1, 'ifindex': 12, 'napi-id': 594, 'type': 'rx'}, {'id': 2, 'ifindex': 12, 'napi-id': 595, 'type': 'rx'}, {'id': 3, 'ifindex': 12, 'napi-id': 596, 'type': 'rx'}, {'id': 0, 'ifindex': 12, 'napi-id': 593, 'type': 'tx'}, {'id': 1, 'ifindex': 12, 'napi-id': 594, 'type': 'tx'}, {'id': 2, 'ifindex': 12, 'napi-id': 595, 'type': 'tx'}, {'id': 3, 'ifindex': 12, 'napi-id': 596, 'type': 'tx'}] $ ./cli.py --spec netdev.yaml --do napi-get --json='{"id": 593}' {'id': 593, 'ifindex': 12, 'irq': 291, 'pid': 3727} $ ./cli.py --spec netdev.yaml --dump napi-get --json='{"ifindex": 12}' [{'id': 596, 'ifindex': 12, 'irq': 294, 'pid': 3724}, {'id': 595, 'ifindex': 12, 'irq': 293, 'pid': 3725}, {'id': 594, 'ifindex': 12, 'irq': 292, 'pid': 3726}, {'id': 593, 'ifindex': 12, 'irq': 291, 'pid': 3727}] ==================== Link: https://lore.kernel.org/r/170147307026.5260.9300080745237900261.stgit@anambiarhost.jf.intel.comSigned-off-by:
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Jakub Kicinski authored
Make bnxt compatible with the newly added netlink queue GET APIs. Signed-off-by:
Amritha Nambiar <amritha.nambiar@intel.com> Reviewed-by:
Michael Chan <michael.chan@broadcom.com> Link: https://lore.kernel.org/r/170147336340.5260.6773000274196548907.stgit@anambiarhost.jf.intel.comSigned-off-by:
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Amritha Nambiar authored
In the threaded NAPI mode, expose the PID of the NAPI thread. Signed-off-by:
Sridhar Samudrala <sridhar.samudrala@intel.com> Link: https://lore.kernel.org/r/170147335818.5260.10253384006102593087.stgit@anambiarhost.jf.intel.comSigned-off-by:
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for PID of the NAPI thread. Add code generated from the spec. Signed-off-by:
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Amritha Nambiar authored
Add support to associate the interrupt vector number for a NAPI instance. Signed-off-by:
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for interrupt number among the NAPI attributes. Add code generated from the spec. Signed-off-by:
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Amritha Nambiar authored
Implement the netdev netlink framework functions for napi support. The netdev structure tracks all the napi instances and napi fields. The napi instances and associated parameters can be retrieved this way. Signed-off-by:
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for napi related information. Add code generated from the spec. Signed-off-by:
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Amritha Nambiar authored
Implement the netdev netlink framework functions for exposing queue information. Signed-off-by:
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Amritha Nambiar authored
After the napi context is initialized, map the napi instance with the queue/queue-set on the corresponding irq line. Signed-off-by:
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Amritha Nambiar authored
Add the napi pointer in netdev queue for tracking the napi instance for each queue. This achieves the queue<->napi mapping. Signed-off-by:
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Amritha Nambiar authored
Add support in netlink spec(netdev.yaml) for queue information. Add code generated from the spec. Note: The "queue-type" attribute takes values 0 and 1 for rx and tx queue type respectively. Signed-off-by:
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- 04 Dec, 2023 22 commits
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Jakub Kicinski authored
Michael Chan says: ==================== bnxt_en: Support new 5760X P7 devices This series completes the basic support for the new 5760X P7 devices with new PCI IDs added in the last patch. Thie first patch fixes a backing store issue introduced in the last patchset last week. The 2nd patch is the new firmware interface required to support the new chips. The next few patches are doorbell changes, refactoring, and new hardware interface structures. New changes to support packet reception including TPA are added in patch 10. The next 4 patches are ethernet link related changes to support the new chip. ==================== Link: https://lore.kernel.org/r/20231201223924.26955-1-michael.chan@broadcom.comSigned-off-by:
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Michael Chan authored
Now with basic support for the new chip family, add the PCI IDs of the new devices. Reviewed-by:
Andy Gospodarek <gospo@broadcom.com> Signed-off-by:
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Michael Chan authored
Add new look up entries to convert the new supported speeds, advertised speeds, etc to ethtool link modes. Reviewed-by:
Damodharam Ammepalli <damodharam.ammepalli@broadcom.com> Signed-off-by:
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Michael Chan authored
Modify bnxt_force_link_speed() to support the new speeds stored in link_info->support_speeds2, including the new 400G speed. Reviewed-by:
Ajit Khaparde <ajit.khaparde@broadcom.com> Signed-off-by:
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Michael Chan authored
Newer firmware supporting PAM4 112Gbps speeds use new parameters in firmware message structures. Detect the new firmware capability and add basic logic to report and store these new fields. Reviewed-by:
Hongguang Gao <hongguang.gao@broadcom.com> Reviewed-by:
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Michael Chan authored
Add helper functions to refactor the logic that converts firmware speed masks to ethtool speeds. Pass the phy_flags to bnxt_get_ethtool_speeds() and the call chain. The refactoring and the phy_flags will be needed when adding support for the new speeds in the next patches. Reviewed-by:
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Michael Chan authored
These new completion types are supported on the new P7 chips. These new types have commonalities with the legacy types. After the refactoring, we mainly have to add new functions to handle the the new meta data formats and the RX hash information in the new types. Signed-off-by:
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Michael Chan authored
Refactor bnxt_tpa_start() by adding bnxt_tpa_metadata() to gather the metadata from the TPA_START completion. This makes it easier to support the new P7 chip which has a modified TPA_START completion structure with different metadata formats. We also add vlan_valid and cfa_code_valid fields to the bnxt_tpa_info structure so that the VLAN and VF rep logic can be common for all chips. The VLAN metadata is now collected in bnxt_tpa_start() only when it is valid and the vlan_valid field will be set. bnxt_tpa_end() can now use common VLAN logic for all chips. Signed-off-by:
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Michael Chan authored
Refactor the logic in the RX path that checks for the accelerated VLAN tag by adding a new function. This will make it easier to support the new receive logic on P7 chips. Reviewed-by:
Pavan Chebbi <pavan.chebbi@broadcom.com> Signed-off-by:
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Michael Chan authored
Add new RX, TX, and TPA hardware interface structures and macros for the P7 chips. Reviewed-by:
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Ajit Khaparde authored
Add a new rss_cap field in the per device struct bnxt and move all the RSS capability fields there. It will be easier to add new RSS capabilities for the new P7 chips. Signed-off-by:
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Michael Chan authored
The new chip family passes the Toggle bits to the driver in the NQE notification. The driver now stores this value and sends it back to hardware when it re-arms the RX and TX CQs. Together with the earlier patch that guarantees the driver will only re-arm the CQ at the end of NAPI polling if it has seen a new NQE, this method allows the hardware to detect any dropped doorbells. Signed-off-by:
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Hongguang Gao authored
The doorbell offset on P5 chips is hard coded. On the new P7 chips, it is returned by the firmware. Simplify the logic that determines this offset and store it in a new db_offset field in struct bnxt. Also, provide this offset to the RoCE driver in struct bnxt_en_dev. Reviewed-by:
Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by:
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Michael Chan authored
Repurpose the BNXT_FLAG_CHIP_SR2 flag by renaming it to BNXT_FLAG_CHIP_P7 since the SR2 chip never went to production. The SR2 statictics structure is also renamed for the P7 chip. Define the basic P7 doorbell bits (Epoch. Toggle, etc) and implement the Epoch bit logic. The next higher bit beyond the legal doorbell mask is the Epoch bit used for doorbells on P7 chips. This bit is used by the chip to detect dropped doorbells. The 57608 chip ID belonging to the P7 family is also defined. Note that the PCI ID is not added until the last patch in the series. Signed-off-by:
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Michael Chan authored
This updated interface supports the new 5760X P7 chip family. It has the changes to support the new link speeds/modes and other changes for the basic L2 features. Signed-off-by:
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Michael Chan authored
The current code determines the last backing store valid type during bnxt_hwrm_func_backing_store_qcaps_v2(). In effect, the last type is determined based on what firmware advertises. The more correct way is to determine it based on what the driver is configuring. The driver may not configure all the backing store types advertised by firmware. Move the logic to determine the last type to bnxt_backing_store_cfg_v2(). We need to pass the legacy enable flags to the function in case only the legacy types are being configured. Fixes: 236e237f ("bnxt_en: Add support for HWRM_FUNC_BACKING_STORE_CFG_V2 firmware calls") Signed-off-by:
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Guillaume Nault authored
Walk the hashinfo->bhash2 table so that inet_diag can dump TCP sockets that are bound but haven't yet called connect() or listen(). The code is inspired by the ->lhash2 loop. However there's no manual test of the source port, since this kind of filtering is already handled by inet_diag_bc_sk(). Also, a maximum of 16 sockets are dumped at a time, to avoid running with bh disabled for too long. There's no TCP state for bound but otherwise inactive sockets. Such sockets normally map to TCP_CLOSE. However, "ss -l", which is supposed to only dump listening sockets, actually requests the kernel to dump sockets in either the TCP_LISTEN or TCP_CLOSE states. To avoid dumping bound-only sockets with "ss -l", we therefore need to define a new pseudo-state (TCP_BOUND_INACTIVE) that user space will be able to set explicitly. With an IPv4, an IPv6 and an IPv6-only socket, bound respectively to 40000, 64000, 60000, an updated version of iproute2 could work as follow: $ ss -t state bound-inactive Recv-Q Send-Q Local Address:Port Peer Address:Port Process 0 0 0.0.0.0:40000 0.0.0.0:* 0 0 [::]:60000 [::]:* 0 0 *:64000 *:* Reviewed-by:
Eric Dumazet <edumazet@google.com> Signed-off-by:
Guillaume Nault <gnault@redhat.com> Reviewed-by:
Kuniyuki Iwashima <kuniyu@amazon.com> Link: https://lore.kernel.org/r/b3a84ae61e19c06806eea9c602b3b66e8f0cfc81.1701362867.git.gnault@redhat.comSigned-off-by:
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Jakub Kicinski authored
Heiko Stuebner says: ==================== net: phy: micrel: additional clock handling Some Micrel phys define a specific rmii-ref clock (added in 2014) while the generic phy binding specifies an unnamed clock for ethernet phys. This allows Micrel phys to use both, so as to keep the phys not using the named rmii-ref clock to conform to the generic binding while allowing them to enable a supplying clock, when the phy is not supplied by a dedicated oscillator. ==================== Link: https://lore.kernel.org/r/20231201150131.326766-1-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
The generic ethernet-phy binding allows describing an external clock since commit 350b7a25 ("dt-bindings: net: phy: Document support for external PHY clk") for cases where the phy is not supplied by an oscillator but instead by a clock from the host system. And the old named "rmii-ref" clock from 2014 is only specified for phys of the KSZ8021, KSZ8031, KSZ8081, KSZ8091 types. So allow retrieving and enabling the optional generic clock on phys that do not provide a rmii-ref clock. Signed-off-by:
Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20231201150131.326766-3-heiko@sntech.deSigned-off-by:
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Heiko Stuebner authored
While the external clock input will most likely be enabled, it's not guaranteed and clk_get_rate in some suppliers will even just return valid results when the clock is running. So use devm_clk_get_optional_enabled to retrieve and enable the clock in one go. Signed-off-by:
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Jiri Pirko authored
In case NLMSG_DONE message is sent as a reply to doit action, multiple kernel implementation do not send anything else than struct nlmsghdr. Add this note to the Netlink intro documentation. Signed-off-by:
Jiri Pirko <jiri@nvidia.com> Reviewed-by:
Bagas Sanjaya <bagasdotme@gmail.com> Link: https://lore.kernel.org/r/20231201180154.864007-1-jiri@resnulli.usSigned-off-by:
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David S. Miller authored
Suman Ghosh says: ==================== octeontx2: Multicast/mirror offload changes This patchset includes changes to support TC multicast/mirror offload. Patch #1: Adds changes to support new mailbox to offload multicast/mirror offload. Patch #2: Adds TC related changes which uses the newly added mailboxes to offload multicast/mirror rules. ==================== Signed-off-by:David S. Miller <davem@davemloft.net>
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