- 26 Oct, 2020 7 commits
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Dmytro Laktyushkin authored
[Why&How] Create a separate dcn21_fast_validate_bw function for dcn21. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Sung Lee authored
[WHY] DF PState and Voltage State are coupled such that one cannot be raised without raising the other. This uses more power than is necessary in high bandwidth scenarios. [HOW] Add logic to create a new bounding box state that allows for DF PState to be low while Voltage State is high. Watermarks vlevel calculation logic was also udpated to assume state 1 contains the new optimized state. Signed-off-by:
Sung Lee <sung.lee@amd.com> Acked-by:
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Christian König authored
Merge the functionality mostly into amdgpu_vm_bo_update_mapping. This way we can even handle small contiguous system pages without to much extra CPU overhead. v2: fix typo, keep the cursor as it is for now Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com> (v1) Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Ideally this should be a multiple of the VM block size. 2MB should at least fit for Vega/Navi. Signed-off-by:
Madhav Chauhan <madhav.chauhan@amd.com> Reviewed-by:
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Tao Zhou authored
Per PMFW 59.9.0. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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John Clements authored
loaded fw can be queried from sys fs interface Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Xiaomeng Hou authored
enable IP discovery for vangogh. Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by:
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- 23 Oct, 2020 15 commits
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David Galiffi authored
[why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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xinhui pan authored
Size is page count here. Reviewed-by:
xinhui pan <xinhui.pan@amd.com> Signed-off-by:
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Mauro Carvalho Chehab authored
dm_comressor_info -> dm_compressor_info The kernel-doc markup is right, but the struct itself and their references contain a typo. Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by:
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Mauro Carvalho Chehab authored
Some functions have different names between their prototypes and the kernel-doc markup. Acked-by:
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Mauro Carvalho Chehab authored
A kernel-doc markup can't be mixed with a random comment, as it causes parsing problems. While here, change an invalid kernel-doc markup into a common comment. Acked-by:
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Harish Kasiviswanathan authored
Workaround to fix the soft hang observed in certain compute applications. Acked-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by:
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Madhav Chauhan authored
2MB area is reserved at top inside VM. Suggested-by:
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Bhawanpreet Lakha authored
Enable Memory Access at Last Level (MALL) feature for display. v2: squash in 64 bit division fixes Signed-off-by:
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Likun Gao authored
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid. v2: drop module option. We need to add UAPI so userspace can request MALL per buffer. Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Alex Deucher authored
This adds the NOALLOC registers. Signed-off-by: -
Tom Rix authored
A break is not needed if it is preceded by a return or break Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Tom Rix <trix@redhat.com> Signed-off-by:
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Tianci.Yin authored
Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
The blockchain SKU has no display and video support, remove them. Reviewed-by:
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Likun Gao authored
Skip disabled sa to correct the cu_info and active_rbs for sienna cichlid. Signed-off-by:
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Kenneth Feng authored
if it's fine-grained clock dpm, remove the average clock value and reflects the real clock. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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- 21 Oct, 2020 15 commits
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Mauro Carvalho Chehab authored
Running "make htmldocs: produce lots of warnings on those files: ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:177: warning: Excess function parameter 'p_size' description in 'amdgpu_vram_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:211: warning: Excess function parameter 'man' description in 'amdgpu_vram_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:90: warning: Excess function parameter 'p_size' description in 'amdgpu_gtt_mgr_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c:134: warning: Excess function parameter 'man' description in 'amdgpu_gtt_mgr_fini' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' ./drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:675: warning: Excess function parameter 'dev' description in 'amdgpu_device_asic_init' They're related to the repacement of some parameters by adev, and due to a few renamed parameters. While here, uniform the name of the parameter for it to be the same on all functions using a pointer to struct amdgpu_device. Update the kernel-doc documentation accordingly. Signed-off-by:
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Sumera Priyadarsini authored
Return statements for functions returning bool should use truth and false instead of 1 and 0 respectively. Modify cik_event_interrupt.c to return false instead of 0. Issue found with Coccinelle. Signed-off-by:
Sumera Priyadarsini <sylphrenadin@gmail.com> Signed-off-by:
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Yifan Zhang authored
[Why] Screen corruption on Navi10 card [How] Set system context in DCN only on Renoir Tested-by:
Matt Coffin <mcoffin13@gmail.com> Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Roman Li <Roman.Li@amd.com> Signed-off-by:
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Kenneth Feng authored
fclk value is missing in pp_dpm_fclk. add this to correctly show the current value. Signed-off-by:
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John Clements authored
This reverts commit 265c280a. Reviewed-by:
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Kenneth Feng authored
fix the wrong fan speed in fan1_input when the fan control mode is manual. the fan speed value is not correct when we set manual mode to fan1_enalbe - 1. since the fan speed in the metrics table always reflects the real fan speed,we can fetch the fan speed for both auto and manual mode. Signed-off-by:
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Bas Nieuwenhuizen authored
As far a I can tell uses a variant of DCN3xx which uses num_pkrs. If we do not initialize the variable we will set the register field to ilog2(0) = -1, though the mask will reduce that to 7. Pretty sure 7 is not the value we want here. Signed-off-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Reviewed-and-Tested-by:
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Likun Gao authored
Update driver if file for sienna cichlid. Signed-off-by:
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Likun Gao authored
Fix the function used for sienna cichlid to get correct PCIE information by pp_dpm_pcie. Signed-off-by:
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Alex Deucher authored
Sienna Cichlid and newer have a hw fix so no longer require the workaround. Reviewed-by:
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Chengming Gui authored
set noretry default value to 1 for sienna_cichlid/navy_founder/dimgrey_cavefish. Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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Boyuan Zhang authored
Enable VCN 3.0 PG and CG for Vangogh by setting up flags. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
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Jay Cornwall authored
0 causes instruction fetch stall at cache line boundary under some conditions on Navi10. A non-zero prefetch is the preferred default in any case. Fixes soft hang in Luxmark. Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
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Kevin Wang authored
1. when smc feature bit isn't mapped, the feature state isn't showed on sysfs node of pp_features. 2. add pp_features table title Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Dennis Li authored
because i2c is unstable in GPU reset, driver need protect eeprom update from GPU reset, to not miss any bad page record. Signed-off-by:
Dennis Li <Dennis.Li@amd.com> Reviewed-by:
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- 16 Oct, 2020 3 commits
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Alex Deucher authored
Add a helper so we can set per asic default values. Also, the module parameter is currently clamped to 8, but clamp it per asic just in case some asics have different limits in the future. Enable the option on gfx6,7 as well for consistency. Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
psp sysfs not cleaned up on driver unload for sienna_cichlid Fixes: ce87c98d ("drm/amdgpu: Include sienna_cichlid in USBC PD FW support.") Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Some setups will fail to build. So copy dcn301 makefile setup which is known to work Signed-off-by:
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