- 06 Sep, 2013 2 commits
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Ralf Baechle authored
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Jerin Jacob authored
The use of current_cpu_type() in cpu_is_noncoherent_r10000() is not preemption-safe. Use boot_cpu_type() instead to make it preemption-safe. <log> / # insmod mtd_readtest.ko dev=4 mtd_readtest: MTD device: 4 mtd_readtest: MTD device size 996671488, eraseblock size 524288, page size 4096, count of eraseblocks 1901, pages per eraseblock 128, OOB size 224 mtd_readtest: scanning for bad eraseblocks mtd_readtest: scanned 1901 eraseblocks, 0 are bad mtd_readtest: testing page read BUG: using smp_processor_id() in preemptible [00000000] code: insmod/99 caller is mips_dma_sync_single_for_cpu+0x2c/0x128 CPU: 2 PID: 99 Comm: insmod Not tainted 3.10.4 #67 Stack : 00000006 69735f63 00000000 00000000 00000000 00000000 808273d6 00000032 80820000 00000002 8d700000 8de48fa0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 8d6afb00 8d6afb24 80721f24 807b9927 8012c130 80820000 80721f24 00000002 00000063 8de48fa0 8082333c 807b98e6 8d6afaa0 ... Call Trace: [<80109984>] show_stack+0x64/0x7c [<80666230>] dump_stack+0x20/0x2c [<803a2210>] debug_smp_processor_id+0xe0/0xf0 [<801116f0>] mips_dma_sync_single_for_cpu+0x2c/0x128 [<8043456c>] nand_plat_read_page+0x16c/0x234 [<8042fad4>] nand_do_read_ops+0x194/0x480 [<804301dc>] nand_read+0x50/0x7c [<804261c8>] part_read+0x70/0xc0 [<804231dc>] mtd_read+0x80/0xe4 [<c0431354>] init_module+0x354/0x6f8 [mtd_readtest] [<8010057c>] do_one_initcall+0x140/0x1a4 [<80176d7c>] load_module+0x1b5c/0x2258 [<8017752c>] SyS_init_module+0xb4/0xec [<8010f3fc>] stack_done+0x20/0x44 BUG: using smp_processor_id() in preemptible [00000000] code: insmod/99 </log> Signed-off-by:Jerin Jacob <jerinjacobk@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5800/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- 05 Sep, 2013 5 commits
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Ralf Baechle authored
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Prem Mallappa authored
Fixed compilation errors in case of non-KEXEC kernel Rearranging code so that crashk_res gets updated. - crashk_res is updated after mips_parse_crashkernel(), after resource_init(), which is after arch_mem_init(). - The reserved memory is actually treated as Usable memory, Unless we load the crash kernel, everything works. Signed-off-by:
Prem Mallappa <pmallappa@caviumnetworks.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/5805/Signed-off-by:
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Prem Mallappa authored
KDUMP: skip indirection page, as crashkernel has already copied to destination [ralf@linux-mips.org: cosmetic changes.] Signed-off-by:
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Maciej W. Rozycki authored
This change corrects DECstation HRT calibration, by removing the following bugs: 1. Calibration period selection -- HZ / 10 has been chosen, however on DECstation computers, HZ never divides by 10, as the choice for HZ is among 128, 256 and 1024. The choice therefore results in a systematic calibration error, e.g. 6.25% for the usual choice of 128 for HZ: 128 / 10 * 10 = 120 (128 - 120) / 128 -> 6.25% The change therefore makes calibration use HZ / 8 that is always accurate for the HZ values available, getting rid of the systematic error. 2. Calibration starting point synchronisation -- the duration of a number of intervals between DS1287A periodic interrupt assertions is measured, however code does not ensure at the beginning that the interrupt has not been previously asserted. This results in a variable error of e.g. up to another 6.25% for the period of HZ / 8 (8.(3)% with the original HZ / 10 period) and the usual choice of 128 for HZ: 1 / 16 -> 6.25% 1 / 12 -> 8.(3)% The change therefore adds an initial call to ds1287_timer_state that clears any previous periodic interrupt pending. The same issue applies to both I/O ASIC counter and R4k CP0 timer calibration on DECstation systems as similar code is used in both cases and both pieces of code are covered by this fix. On an R3400 test system used this fix results in a change of the I/O ASIC clock frequency reported from values like: I/O ASIC clock frequency 23185830Hz to: I/O ASIC clock frequency 24999288Hz removing the miscalculation by 6.25% from the systematic error and (for the individual sample provided) a further 1.00% from the variable error, accordingly. The nominal I/O ASIC clock frequency is 25MHz on this system. Here's another result, with the fix applied, from a system that has both HRTs available (using an R4400 at 60MHz nominal): MIPS counter frequency 59999328Hz I/O ASIC clock frequency 24999432Hz Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5807/Signed-off-by:
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Geert Uytterhoeven authored
ERROR: "copy_from_user_page" [drivers/staging/lustre/lustre/libcfs/libcfs.ko] undefined! Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5808/Signed-off-by:
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- 04 Sep, 2013 13 commits
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Ralf Baechle authored
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Gabor Juhos authored
The Ralink RT3883 SoCs have a built-in PCI Host Controller device. The patch adds a platform driver and device tree binding documentation for that. The patch also enables the HW_HAS_PCI config option. This is required in order to be able to enable the PCI support. Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Acked-by:
John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5758/Signed-off-by:
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Jim Quinlan authored
The BMIPS5000 (Zephyr) processor utilizes instruction speculation. A stale misprediction address in either the JTB or the CRS may trigger a prefetch inside a region that is currently being used by a DMA engine, which is not IO-coherent. This prefetch will fetch a line into the scache, and that line will soon become stale (ie wrong) during/after the DMA. Mayhem ensues. In dma-default.c, the r10000 is handled as a special case in the same way that we want to handle Zephyr. So we generalize the exception cases into a function, and include Zephyr as one of the processors that needs this special care. Signed-off-by:
Jim Quinlan <jim2101024@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5776/Signed-off-by:
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John Crispin authored
Add a helper for reseting different devices on the SoC. Signed-off-by:
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Gabor Juhos authored
Override certain CPU features to help GCC to optimize the generated code. Saves about 150KB in the vmlinux image with a generic configuration. text data bss dec hex filename 3824158 134820 234192 41931702 3ffb92 vmlinux.no-override 3664054 138804 234192 4037050 3d99ba vmlinux.override Signed-off-by: -
John Crispin authored
Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by:
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John Crispin authored
The watchdog driver of the SoC uses the clk API to get the clock associated with the watchdog device. However the MT7620 specific setup code does not register a clock for the watchdog device yet which leads to the following error: rt2880_wdt: probe of 10000120.watchdog failed with error -2 Register a clock device for the watchdog in order to avoid the error and make the watchdog usable. Signed-off-by:
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Gabor Juhos authored
The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by:
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John Crispin authored
Select the the EHCI and OHCI symbols. Signed-off-by:
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John Crispin authored
Make the code print which of SDRAM, DDR1 or DDR2 was detected. Signed-off-by:
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John Crispin authored
Make plat_time_init() call clocksource_of_init() allowing the systick cevt to load. Signed-off-by:
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John Crispin authored
Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent of the SoC master clock. If we want to automatic frequency scaling to work we need to use the systick timer as the clock source. Signed-off-by:
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John Crispin authored
Adds a driver for the periodic timer found on Ralink SoC. Signed-off-by:
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- 03 Sep, 2013 20 commits
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Ganesan Ramalingam authored
Add a default built-in device tree for XLP2xx SoC. The new file xlp_fvp.dts has updated entries for I2C and memory. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5705/Signed-off-by:
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Ganesan Ramalingam authored
Add USB intialization code to handle the new XLP2XX USB 3.0 block. This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h and xlp/nlm_hal.c is also updated for the new USB block. Signed-off-by:
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Ganesan Ramalingam authored
XLP2xx has a new I2C controller which has 4 buses connected to it. Update the IO offset and IRQ mapping code to reflect this. Signed-off-by:
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Jayachandran C authored
On XLP2xx, wakeup code does not need to enable clock on the core. Update xlp/wakeup.c to handle this. Signed-off-by:
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Ganesan Ramalingam authored
Add code to calculate the CPU and PIC frequency for XLP2XX SoCs. Since the PIC frequency on XLP2XX can be configured, add a new macro pic_timer_freq() to be used in netlogic/common/time.c. Signed-off-by:
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Jayachandran C authored
The config7/config4 register has to be written on all the threads. This does not cause any problems in XLP, but is needed for XLPII Signed-off-by:
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Jayachandran C authored
XLP2XX is first in the series of 28nm XLPII processors. The changes are to: * Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c. * Add a cpu_is_xlpii() function to check for XLPII processors. * Update xlp_mmu_init() to use config4 to enable extended TLB. Signed-off-by:
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Jayachandran C authored
The flash chipselects can span 32MB, fix this in the built-in device tree. Signed-off-by:
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Jayachandran C authored
Do not pass a memory section in the built-in DTB, and let the boot code use the values from the DRAM BARs. Signed-off-by:
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Jayachandran C authored
Read the memory from the Bridge DRAM BARs, if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees. Signed-off-by:
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Gabor Juhos authored
The ath79 code uses static clock devices and provides its own clk_{get,put} implementations. Change the code to use dynamically allocated clock devices and register the clocks within the clkdev framework. Additionally, remove the local clk_{get,put} implementation. The clkdev framework has a common implementation of those. Also move the call of ath79_clock_init() from plat_mem_init() to plat_time_init(). Otherwise it would not be possible to use memory allocation functions from ath79clock_init() becasuse the memory subsystem is not yet initialized when plat_mem_init() runs. Signed-off-by: -
Gabor Juhos authored
Use local variables for ref, cpu, ddr and ahb rates in SoC specific clock init functions. The patch has no functional changes, it is an interim change in preparation of the next patch. Signed-off-by:
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Gabor Juhos authored
Instead of accessing the rate field of the static clock devices directly, use the recently introduced helper function to get the rate of the basic clocks. The static ath79_{ahb,cpu,ddr,ref}_clk variables will be removed by a subsequent patch. The actual change is in preparation of that. Also move the clock frequency printing code into the plat_time_init function. We are getting the cpu clock rate there already so we can save an extra call of the helper. Signed-off-by: -
Gabor Juhos authored
The ath79 platform uses similar code to get the rate of various clocks during init. Separate the similar code into a new helper function and use that to avoid code duplication. Signed-off-by:
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Gabor Juhos authored
The reference clock rate is passed in the first argument of the function. Use that instead of the rate of the global ath79_ref_clk variable. Signed-off-by:
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Felix Fietkau authored
The watchdog device on the AR933x is connected to the AHB clock, however the current code uses the reference clock. Due to the wrong rate, the watchdog driver can't calculate correct register values for a given timeout value and the watchdog unexpectedly restarts the system. The code uses the wrong value since the initial commit 04225e1d (MIPS: ath79: add AR933X specific clock init) The patch fixes the code to use the correct clock rate to avoid the problem. Cc: stable@vger.kernel.org Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
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Gabor Juhos authored
The ath79 code supports various SoCs which are using either a 24Kc or a 74Kc core. The 74Kc core has DSP support, so don't hardwire the values to zero. Commit 00dc5ce2 (MIPS: ath79: don't hardcode the unavailability of the DSP ASE) has fixed this already, but that change got reverted by 47503256 (MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.) Reported-by:
Helmut Schaa <helmut.schaa@googlemail.com> Signed-off-by:
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John Crispin authored
This add a default config for the Lantiq XWAY SoC. Signed-off-by:
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Thomas Langer authored
The clocks of the serial ports were not setup properly. Signed-off-by:
Thomas Langer <thomas.langer@lantiq.com> Acked-by:
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Thomas Langer authored
Add cpu-feature-override.h for the GPON SoC Signed-off-by:
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