- 21 Oct, 2016 2 commits
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Jiri Olsa authored
Adding simple TUI cacheline browser. It triggers when you press 'd' in the main browser on the specific cacheline. It allows to navigate through cacheline's offsets and display callchains (implemented in following patches). Signed-off-by:
Jiri Olsa <jolsa@kernel.org> Tested-by:
Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: David Ahern <dsahern@gmail.com> Cc: Don Zickus <dzickus@redhat.com> Cc: Joe Mario <jmario@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/n/tip-fovjwgyusv3rz5qxk3hnahtl@git.kernel.orgSigned-off-by:
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Jiri Olsa authored
Add the main cachelines TUI browser. It allows to navigate through cachelines and display their details and callchains (implemented in the following patches). Signed-off-by:
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- 19 Oct, 2016 36 commits
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Jiri Olsa authored
Adding the --stdio option output support. The output tables are dumped directly to the stdio. $ perf c2c report ================================================= Shared Data Cache Line Table ================================================= # # Total ----- LLC Load Hitm ----- ---- Store Reference ---- --- Load Dram ---- LLC Total ----- Core Load Hit ----- -- LLC Load Hit -- # Cacheline records %hitm Total Lcl Rmt Total L1Hit L1Miss Lcl Rmt Ld Miss Loads FB L1 L2 Llc Rmt # .................. ....... ....... ....... ....... ....... ....... ....... ....... ........ ........ ....... ....... ....... ....... ....... ........ ........ # 0xffff88000235f840 17 0.00% 0 0 0 17 17 0 0 0 0 0 0 0 0 0 0 ... ================================================= Shared Cache Line Distribution Pareto ================================================= # # ----- HITM ----- -- Store Refs -- Data address ---------- cycles ---------- cpu Shared # Rmt Lcl L1 Hit L1 Miss Offset Pid Tid rmt hitm lcl hitm load cnt Symbol Object Node # ....... ....... ....... ....... .................. ....... ..................... ........ ........ ........ ........ .................... ................. .... # ------------------------------------------------------ 0 0 17 0 0xffff88000235f840 ------------------------------------------------------ 0.00% 0.00% 5.88% 0.00% 0x0 11474 11474:kworker/u16:5 0 0 0 1 [k] rmap_walk_file [kernel.kallsyms] 0 0.00% 0.00% 5.88% 0.00% 0x10 11474 11474:kworker/u16:5 0 0 0 1 [k] lock_page_memcg [kernel.kallsyms] 0 0.00% 0.00% 11.76% 0.00% 0x20 11474 11474:kworker/u16:5 0 0 0 1 [k] page_mapping [kernel.kallsyms] 0 0.00% 0.00% 64.71% 0.00% 0x28 11474 11474:kworker/u16:5 0 0 0 1 [k] __test_set_page_writeback [kernel.kallsyms] 0 0.00% 0.00% 11.76% 0.00% 0x30 11474 11474:kworker/u16:5 0 0 0 1 [k] page_mapped [kernel.kallsyms] 0 ... Signed-off-by: -
Jiri Olsa authored
Set resort/display fields for both cachelines and single cacheline displays. Cachelines are sorted on: rmt_hitm will be made configurable in following patches. Following fields are display for cachelines: dcacheline tot_recs percent_hitm tot_hitm,lcl_hitm,rmt_hitm stores,stores_l1hit,stores_l1miss dram_lcl,dram_rmt ld_llcmiss tot_loads ld_fbhit,ld_l1hit,ld_l2hit ld_lclhit,ld_rmthit The single cacheline is sort by: offset,rmt_hitm,lcl_hitm will be made configurable in following patches. Following fields are display for each cacheline: percent_rmt_hitm percent_lcl_hitm percent_stores_l1hit percent_stores_l1miss offset pid tid mean_rmt mean_lcl mean_load cpucnt symbol dso node Signed-off-by:
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Jiri Olsa authored
Allow to setup number of header lines for c2c hists objects. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: cl_srcline It displays source line related to the code address that accessed cacheline. It's a wrapper to global srcline sort entry. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: cpucnt It displays number of distinct cpus that hit cacheline. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: median, mean_rmt, mean_lcl, mean_load, stddev It displays statistics hits related to cacheline accesses. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: node It displays nodes hits related to cacheline accesses. The node filed comes in 3 flavors: - node IDs separated by ',' - node IDs with stats for each ID, in following format: Node{cpus %hitms %stores} - node IDs with list of affected CPUs in following format: Node{cpu list} User can switch the flavor with -N option (-NN,-NNN). It will be available in TUI to switch this with 'n' key. Signed-off-by: -
Jiri Olsa authored
They are to be displayed in the single cacheline output: symbol, dso They are wrappers for global sort_sym and sort_dso sort entries with c2c specific headers. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: tid It's a wrapper for global sort_thread sort entry with c2c specific header. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: pid We currently don't have a single 'pid' sort/display entry, which would output just pid number, hence adding it into c2c code. Signed-off-by:
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Jiri Olsa authored
They are to be displayed in the main cachelines overall output: dram_lcl, dram_rmt They display DRAM rmt/lcl access numbers for specific cacheline. Signed-off-by:
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Jiri Olsa authored
They are to be displayed in the single cacheline output: percent_rmt_hitm, percent_lcl_hitm, percent_stores_l1hit, percent_stores_l1miss They display percentage of HITMs/stores for specific offset in the cacheline. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: percent_hitm It displays HITMs percentage for cacheline. It counts remote HITMs at the moment, but it is changed later to support local as well, based on the sort configuration. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: tot_loads It displays sum of all load accesses for cacheline. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: tot_recs It displays sum of all cachelines accesses. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: ld_llcmiss It displays bare number of LLC misses for cacheline. Signed-off-by:
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Jiri Olsa authored
Add 2 LLC load related dimension key wrappers. They are to be displayed in the main cachelines overall output: ld_lclhit, ld_rmthit They display bare numbers of LLC and remote loads for cacheline. Signed-off-by:
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Jiri Olsa authored
Add 3 loads related dimension key wrappers. They are to be displayed in the main cachelines overall output: ld_fbhit, ld_l1hit, ld_l2hit They all display bare numbers of loads for FB (Fill Buffer), L1 and L2 cache. Signed-off-by:
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Jiri Olsa authored
Add 5 stores related dimension key wrappers. First 3 are to be displayed in the main cachelines overall output: stores, stores_l1hit, stores_l1miss The latter 2 are to be displayed within single cacheline output: cl_stores_l1hit, cl_stores_l1miss They all display bare numbers of stores for cacheline or its related offsets. Signed-off-by:
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Jiri Olsa authored
Adding 5 hitm related dimension key wrappers. First 3 are to be displayed in the main cachelines overall output: tot_hitm, lcl_hitm, rmt_hitm The latter 2 are to be displayed within single cacheline output: cl_rmt_hitm, cl_lcl_hitm They all display bare numbers of remote/local/total HITMs for cacheline or its related offsets. Signed-off-by:
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Jiri Olsa authored
It displays the code address (as hex number) responsible for the accesses. Using c2c wrapper to standard 'symbol_iaddr' object to define own header and simple (just address) code address output. Signed-off-by:
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Jiri Olsa authored
It displays cacheline offset as hex number. Signed-off-by:
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Jiri Olsa authored
It displays cacheline address as hex number. Using c2c wrapper to standard 'dcacheline' object to defined own header and simple (just address) cacheline output. Signed-off-by:
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Jiri Olsa authored
Adding helping macros to define header objects. It will be used in following patches, that add new dimensions. The c2c report will support 2 line headers, hence we only define line[0/1] in macros. Signed-off-by:
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Jiri Olsa authored
Decoding and storing c2c_stats for each hist entry. Changing related function to work with c2c_* objects. Signed-off-by:
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Jiri Olsa authored
Store cacheline related entries in nested hist object for each cacheline data. Nested entries are sorted by 'offset' within related cacheline. We will allow specific sort keys to be configured for nested cacheline data entries in following patches. Signed-off-by:
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Jiri Olsa authored
Adding basic sample processing specific hist_entry allocation callbacks (via hists__add_entry_ops). Overloading 'struct hist_entry' object with new 'struct c2c_hist_entry'. The new hist entry object will carry specific stats and nested hists objects. Signed-off-by:
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Jiri Olsa authored
Fallback to standard dimensions in case we don't find the dimension within c2c ones. Signed-off-by:
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Jiri Olsa authored
Allow to reuse 'struct sort_entry' objects within c2c dimension support. In case the 'struct sort_entry' object meets the need of c2c report we will use it directly in following patches. Signed-off-by:
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Jiri Olsa authored
Adding bare bones of dimension support for c2c report. Main interface functions are: c2c_hists__init c2c_hists__reinit which re/initialize 'struct c2c_hists' object with sort/display entries string, in a similar way that setup_sorting function does. We overload the dimension to provide multi line header support for sort/display entries. Also we overload base 'struct perf_hpp_fmt' object with 'struct c2c_fmt' to define c2c specific functions to deal with multi line headers and spans. Signed-off-by:
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Jiri Olsa authored
Adding c2c report subcommand. It reads the perf.data and displays shared data analysis. This patch adds report basic wirings. It gets fully implemented in following patches. Signed-off-by:
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Jiri Olsa authored
Adding c2c record subcommand. It setups options related to HITM cacheline analysis and calls standard perf record command. $ sudo perf c2c record -v -- -a calling: record -W -d --sample-cpu -e cpu/mem-loads,ldlat=30/P -e cpu/mem-stores/P -a ... It produces perf.data, which is to be reported by perf c2c report, that comes in following patches. Details are described in the man page, which is added in one of the following patches. Committer notes: Testing it: # perf c2c record -a sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 5.050 MB perf.data (412 samples) ] # ls -la perf.data -rw-------. 1 root root 5301752 Oct 4 13:32 perf.data # perf evlist cpu/mem-loads,ldlat=30/P cpu/mem-stores/P # perf evlist -v cpu/mem-loads,ldlat=30/P: type: 4, size: 112, config: 0x1cd, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, mmap: 1, comm: 1, freq: 1, task: 1, precise_ip: 3, mmap_data: 1, sample_id_all: 1, mmap2: 1, comm_exec: 1, { bp_addr, config1 }: 0x1f cpu/mem-stores/P: type: 4, size: 112, config: 0x82d0, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, freq: 1, precise_ip: 3, sample_id_all: 1 # # perf report --stdio <SNIP> # Total Lost Samples: 14 # Samples: 216 of event 'cpu/mem-loads,ldlat=30/P' # Event count (approx.): 15207 # Overhead Symbol Shared Object # ........ ..................................... ............................ 10.32% [k] update_blocked_averages [kernel.vmlinux] 3.43% [.] 0x00000000001a2122 qemu-system-x86_64 (deleted) 2.52% [k] enqueue_entity [kernel.vmlinux] 1.88% [.] g_main_context_query libglib-2.0.so.0.4800.2 1.86% [k] __schedule [kernel.vmlinux] <SNIP> # Samples: 196 of event 'cpu/mem-stores/P' # Event count (approx.): 14771346 # Overhead Symbol Shared Object # ........ ................................... ............................ 13.91% [k] intel_idle [kernel.vmlinux] 3.02% [.] 0x00000000022f06ea chrome 2.94% [.] 0x00000000001a1b4c qemu-system-x86_64 (deleted) 2.94% [.] 0x000000000019d8e4 qemu-system-x86_64 (deleted) 2.38% [.] 0x00000000001a1c52 qemu-system-x86_64 (deleted) <SNIP> Signed-off-by: -
Jiri Olsa authored
Adding c2c command base wirings. Its implementation is going to be added gradually in following patches. Signed-off-by:
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Jiri Olsa authored
Introducing c2c_add_stats function helper to cumulate c2c_stats. Original-patch-by:
Dick Fowles <rfowles@redhat.com> Original-patch-by:
Don Zickus <dzickus@redhat.com> Signed-off-by:
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Jiri Olsa authored
Introducing c2c_decode_stats function, which decodes data_src data into new struct c2c_stats. Signed-off-by:
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Ingo Molnar authored
Merge tag 'perf-vendor_events-for-mingo-20161018' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core Pull perf/vendor_events event tables from Arnaldo Carvalho de Melo: - Add JSON files with vendor event naming for Intel and Power8 processors, allowing users of tools like oprofile to keep using the event names they are used to, as well as people reading vendor documentation, where such naming is used. (Andi Kleen, Sukadev Bhattiprolu) Signed-off-by:
Ingo Molnar <mingo@kernel.org>
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- 18 Oct, 2016 2 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fsLinus Torvalds authored
Pull f2fs bugfix from Jaegeuk Kim: "This fixes a bug which referenced the wrong pointer, sum_page, in f2fs_gc. It was newly introduced in 4.9-rc1. * tag 'for-f2fs-4.9-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs: f2fs: fix wrong sum_page pointer in f2fs_gc
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Ingo Molnar: "Misc fixes, plus hw-enablement changes: - fix persistent RAM handling - remove pkeys warning - remove duplicate macro - fix debug warning in irq handler - add new 'Knights Mill' CPU related constants and enable the perf bits" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel/uncore: Add Knights Mill CPUID perf/x86/intel/rapl: Add Knights Mill CPUID perf/x86/intel: Add Knights Mill CPUID x86/cpu/intel: Add Knights Mill to Intel family x86/e820: Don't merge consecutive E820_PRAM ranges pkeys: Remove easily triggered WARN x86: Remove duplicate rtit status MSR macro x86/smp: Add irq_enter/exit() in smp_reschedule_interrupt()
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