- 22 Mar, 2023 2 commits
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Neil Armstrong authored
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-7-552f3b721f9e@linaro.org
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Neil Armstrong authored
Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by:
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- 20 Mar, 2023 3 commits
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Bhupesh Sharma authored
Normally the 'pinctrl' properties of a SDHC controller and the chip detect pin settings are dependent on the type of the slots (for e.g uSD card slot), regulators and GPIO(s) available on the board(s). So, move the same from the sm6115 dtsi file to the respective board file(s). Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Bhupesh Sharma authored
Normally the 'maximum-speed' and 'dr_mode' properties of a USB controller + port is dependent on the type of the ports, regulators and mode change interrupt routing available on the board(s). So, move the same from the sm6115 dtsi file to respective board file(s). Reviewed-by:
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Bhupesh Sharma authored
There is only one USB controller present on SM6115 / SM4250 Qualcomm SoC, so drop the numbering used with USB node's label names in the dtsi and the related sm4250-oneplus-billie2.dts. Reviewed-by:
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- 16 Mar, 2023 31 commits
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Johan Hovold authored
Fix the external display controller nodes which erroneously described the controllers as belonging to CX rather than MMCX. Fixes: 19d3bb90 ("arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks") Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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Stephan Gerhold authored
The reg address of the tsens_mode nvmem cell is correct but the unit address does not match (0xec vs 0xef). Fix it. No functional change. Fixes: 24aafd04 ("arm64: dts: qcom: msm8916: specify per-sensor calibration cells") Signed-off-by:
Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by:
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Neil Armstrong authored
Miscellaneous DT fixes to remove spurious blank line and enhance readability. Fixes: ffc50b2d ("arm64: dts: qcom: Add base SM8550 dtsi") Fixes: d7da51db ("arm64: dts: qcom: sm8550: add display hardware devices") Signed-off-by:
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Neil Armstrong authored
The node is incomplete and doesn't need a subnode, add the missing properties and move everything to the root of qup-spi0-cs-state node. Fixes: ffc50b2d ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by:
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Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: sm8250-xiaomi-elish.dtb: gpio-keys: key-vol-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: sm8250-sony-xperia-edo-pdx206.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: sm6115p-lenovo-j606f.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: sdm630-sony-xperia-nile-voyager.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: sc7280-idp.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: msm8998-sony-xperia-yoshino-lilac.dtb: gpio-keys: button-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: msm8998-fxtec-pro1.dtb: gpio-hall-sensors: event-hall-sensor1: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Krzysztof Kozlowski authored
gpio-keys,wakeup is a deprecated property: sm8150-sony-xperia-kumano-bahamut.dtb: gpio-keys: key-camera-focus: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: -
Douglas Anderson authored
The mrbland board was never actually produced and there has been no activity around the board for quite some time. It seems highly unlikely to magically get revived. There should be nobody in need of these device trees, so let's delete them. If somehow the project resurrects itself then we can re-add support, perhaps just for -rev1+. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Reviewed-by:
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Douglas Anderson authored
lazor-rev0 was a pile of parts. While I kept the pile of parts for lazor running on my desk for longer than I usually do, those days are still long past. Let's finally delete support for lazor-rev0. Signed-off-by:
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Douglas Anderson authored
The earliest kingoftown that I could find in my pile of boards was -rev2 and even that revision looks pretty rough (plastics on the case are very unfinished). Though I don't actually have details about how many -rev0 devices were produced, I can't imagine anyone still using one. Let's delete support. Signed-off-by:
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Douglas Anderson authored
The earliest wormdingler I could find in my pile of hardware is -rev1. I believe that -rev0 boards were just distributed as a pile of components with no case. At this point I can't imagine anyone needing to make wormdingler-rev0 work, so let's delete support for it. Signed-off-by:
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Adam Skladowski authored
In order for consumers of RPMCC XO clock to probe successfully their parent needs to be feed with reference clock to obtain proper rate, add fixed xo-board clock and supply it to rpmcc to make consumers happy. Frequency setting is left per board basis just like on other recent trees. Fixes: 0484d3ce ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Fixes: ff7f6d34 ("arm64: dts: qcom: Add support for SONY Xperia X/X Compact") Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> [bjorn: Squashed the two patches] Signed-off-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 6daee406 ("arm64: dts: qcom: sm8350: add PCIe devices") Reported-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: bc6588bc ("arm64: dts: qcom: sm8450: add PCIe1 root device") Fixes: 7b09b1b4 ("arm64: dts: qcom: sm8450: add PCIe0 RC device") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: a1c86c68 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x30200000, 0x32200000, 0x34200000, 0x38200000, 0x3c200000) specified in the ranges property for I/O region. Fixes: 813e8315 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Reported-by:
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Manivannan Sadhasivam authored
To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000, 0x64200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: e53bdfc0 ("arm64: dts: qcom: sm8250: Add PCIe support") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x0c200000, 0x0d200000, 0x0e200000) specified in the ranges property for I/O region. While at it, let's also align the entries. Fixes: ed965ef8 ("arm64: dts: qcom: msm8996: add support to pcie") Reported-by:
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Manivannan Sadhasivam authored
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address (0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 095bbdd9 ("arm64: dts: qcom: ipq6018: Add pcie support") Reported-by:
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Manivannan Sadhasivam authored
For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x10200000, 0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses and align them in a single line. Fixes: 33057e16 ("ARM: dts: ipq8074: Add pcie nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 7d1158c9 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. Fixes: 92e0ee9f ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x1b200000) specified in the ranges property for I/O region. Fixes: b84dfd17 ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes") Reported-by:
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Manivannan Sadhasivam authored
For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 42ad2313 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller") Fixes: 5c538e09 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Reported-by:
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Konrad Dybcio authored
Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct compatibles instead of the placeholder qcom,kryo. Signed-off-by:
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- 15 Mar, 2023 4 commits
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Mao Jinlong authored
Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Acked-by:Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
Mao Jinlong <quic_jinlmao@quicinc.com> Signed-off-by:
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Vincent Guittot authored
While stressing EAS on my dragonboard RB3, I have noticed that LITTLE cores where never selected as the most energy efficient CPU whatever the utilization level of waking task. energy model framework uses its cost field to estimate the energy with the formula: nrg = cost of the selected OPP * utilization / CPU's max capacity which ends up selecting the CPU with lowest cost / max capacity ration as long as the utilization fits in the OPP's capacity. If we compare the cost of a little OPP with similar capacity of a big OPP like : OPP(kHz) OPP capacity cost max capacity cost/max capacity LITTLE 1766400 407 351114 407 863 big 1056000 408 520267 1024 508 This can be interpreted as the LITTLE core consumes 70% more than big core for the same compute capacity. According to [1], LITTLE consumes 10% less than big core for Coremark benchmark at those OPPs. If we consider that everything else stays unchanged, the dynamic-power-coefficient of LITTLE core should be only 53% of the current value: 290 * 53% = 154 Set the dynamic-power-coefficient of CPU0-3 to 154 to fix the energy model. [1] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main Fixes: 0e0a8e35 ("arm64: dts: qcom: sdm845: correct dynamic power coefficients") Signed-off-by:Vincent Guittot <vincent.guittot@linaro.org> Signed-off-by:
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Kathiravan T authored
Add SMEM support by adding required nodes. Signed-off-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Kathiravan T authored
Enable the support for download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Signed-off-by:
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