- 05 Jul, 2018 40 commits
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Tony Cheng authored
use worse case watermark (consider both DCC and VM) to keep golden consistent regardless of DCC Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samson Tam authored
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Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Charlene Liu authored
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Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Tony Cheng authored
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Yongqiang Sun authored
In case of roation, width and height in viewport is difference between viewport and h_active and v_active, while this is not scaling. The right way is check ratios in scaling data, to determine it is a scaling case or not. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
Currently dcn1 will not switch between watermark sets so we can save time by not calculating 3 extra sets. Signed-off-by:
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Dmytro Laktyushkin authored
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Mikita Lipski authored
Moving powerplay functions to a new amdgpu_dm_pp_smu class and cleaning dm_services class from unused headers. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
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Mikita Lipski authored
The driver is expecting clock frequency in kHz, while SMU returns the values in 10kHz, which causes the bandwidth validation to fail Signed-off-by:
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Mikita Lipski authored
Add more cases for dm_pp clks translator into pp clks so we can pass the right structures to the powerplay. Use clks translator instead of massive switch statement. Signed-off-by:
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Mikita Lipski authored
Set the powerplay debug flag to false for both Windows and Linux to allow the calls to pplib. So we can retrieve the clock values from powerplay instead of using default hardcoded values. Signed-off-by:
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Roman Li authored
- Fixing integer overflow bug in wait_for_fbc_state_changed() - Correct the max value of retries for the corresponding warning Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Tony Cheng authored
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Dmytro Laktyushkin authored
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Tony Cheng authored
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David Francis authored
As part of hardware certification, read-write access to the link rate, lane count, voltage swing, pre-emphasis, and PHY test pattern of DP connectors is required. This commit adds debugfs files that will correspond to these values. The file operations are not yet implemented: currently writing or reading them does nothing. Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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Tony Cheng authored
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Wesley Chalmers authored
DML does not calculate chroma values for RQ when surface is not YUV, but DC will unconditionally use the uninitialized values for HW programming. This does not cause visual corruption since HW will ignore garbage chroma values when surface is not YUV, but causes presubmission tests to fail golden value comparison. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Zheng, XueLai(Eric) authored
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XueLai(Eric), Zheng <XueLai.Zheng@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
This will prevent watermarks from lowering when unsafe to do so. Signed-off-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
This fixes incorrect clock caching and by extension fixes the clock reporting. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Charlene Liu authored
Also cleanup command_table2.c. No need for a lot of forward declarations. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Wesley Chalmers authored
To ensure tests continue to pass Signed-off-by:
Shahin Khayyer <Shahin.Khayyer@amd.com> Acked-by:
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Dmytro Laktyushkin authored
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Dmytro Laktyushkin authored
This removes redundant set_bandwidth calls as well as fixes a bug in post_set_address_update where dcn1 would never get to lower clocks. Signed-off-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Dmytro Laktyushkin authored
No functional change. Signed-off-by:
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Dmytro Laktyushkin authored
No functional change. Signed-off-by:
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Dmytro Laktyushkin authored
No functional change. Signed-off-by:
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Dmytro Laktyushkin authored
Cleans up dcn_bw_output to only contain calculated info, actual programmed values will now be stored in respective blocks. Signed-off-by:
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Mikita Lipski authored
Add DCF and FCLK clock case statements for changing raven's clocks for voltage request. Also maintain DCEF clock for DCE120 calls. Signed-off-by:
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Mikita Lipski authored
Change struct pointers to creating structs on a stack. Thats fixing a mistake in a previous patch introducing dm_pplib functions Signed-off-by:
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Yongqiang Sun authored
In case of tg count not equal to FE pipe count, if use pipe count to iterate the tgs, it will cause BSOD. Signed-off-by:
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Dmytro Laktyushkin authored
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