- 20 May, 2024 23 commits
-
-
Cruise authored
[Why] When the link BW is smaller than the request BW, the DP LT just kept running and fallback to lower link config. DP LT just aborted if is_hpd_pending bit is high. But is_hpd_pending bit indicates a new HPD event received. It doesn't mean the HPD is low. [How] Abort the DP LT if the link BW is smaller than the request BW. Remove checking is_hpd_pending bit in DP LT. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Cruise <cruise.hung@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Dillon Varone authored
[WHY&HOW] At the time of block sequence construction, the exact reference DPP/DISP clock is not yet known, so the clock should be passed by reference to the DTO programming function. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
-
Dillon Varone authored
[WHY&HOW] Disable to improve stability for now. Reviewed-by:
-
Alvin Lee authored
[Description] There is a corner case where we're in an ODM config that has recout.x != 0. In these scenarios we have to take into account the extra offset in the ODM adjustment for cursor. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
-
Wenjing Liu authored
[why] A recent change for ODM combine refactor contains a typo which causes ODM combine mode programmed incorrectly. Reviewed-by:
George Shen <george.shen@amd.com> Acked-by:
-
Roman Li authored
[Why] Disable idle optimization for each atomic commit is unnecessary, and can lead to a potential race condition. [How] Remove idle optimization check from amdgpu_dm_atomic_commit_tail() Fixes: 196107eb ("drm/amd/display: Add IPS checks before dcn register access") Cc: stable@vger.kernel.org Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
-
Nicholas Susanto authored
[Why] Missing check for when there is new pipe configuration but both cur_pipe and new_pipe are both populated causing update_state of DSC for that instance not being updated correctly. This causes some display mode changes to cause underflow since DSCCLK is still gated when the display requires DSC. [How] Added another condition in the new pipe addition branch that checks if there is a new pipe configuration and if it is not the same as cur_pipe. cur_pipe does not necessarily have to be NULL to go in this branch. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
-
Roman Li authored
[Why] For debugging and testing purposes. [How] If IPS is supported create ips_status debugfs entry. Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status Reviewed-by:
Jerry Zuo <jerry.zuo@amd.com> Acked-by:
-
Roman Li authored
[Why] Reset the shared dmub firmware region on dmub hw init to start with known state. [How] Memset the shared region to 0 in dmub_hw_init(). Suggested-by:
-
Ilya Bakoulin authored
[Why/How] Need to be able to trigger a DMA load to update 3DLUT contents in MPC. Adding a HWSS function to serve as the trigger. Reviewed-by:
Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
-
Chris Park authored
[Why] DML 2.1 allocates two types of memory in its ctx structure but does not destroy them, causing memory leak whenever DML 2.1 instance is created and destroyed. [How] Deallocate two instances of allocated memory whenever DML 2.1 is destroyed. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Chris Park <chris.park@amd.com> Tested-by:
-
Hersen Wu authored
[Why] Coverity reports NULL_RETURN warning. [How] Add pointer NULL check. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
-
Kenneth Feng authored
update driver-if interface for smu 14.0.2/3 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
-
Rodrigo Siqueira authored
Acked-by:
-
Dillon Varone authored
Need to select DTBCLK and DPREFCLK as DTBCLK_p source according to hardware guidance. Reviewed-by:
-
Harikrishna Revalla authored
[why] Cleaning up the code refactor requires hubbub to be in its own component. [how] Move all DCN401 files under newly created hubbub folder and fixing the makefiles. Reviewed-by:
Harikrishna Revalla <Harikrishna.Revalla@amd.com> Tested-by:
-
Samson Tam authored
[Why] Enable adaptive scaler support for DCN401 [How] - Enable build flag for SPL - Set prefer_easf flag to true - Apply light linear scaling policy based on transfer function and pixel format. Choose between linear or non-linear scaling - Set matrix_mode based on pixel format - Disable ring estimator - Add missing EASF register defines, masks, and writes - Disable EASF if scale ratio or number of taps is unsupported and when bypassing the scaler - Add debug flags and registry keys for debugging SPL and EASF - Add support for Visual Confirm with EASF Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
-
Alex Hung authored
This fixes indentations and adjust spaces for better readability and code styles. Reviewed-by:
Alex Hung <alex.hung@amd.com> Tested-by:
-
Chris Park authored
[Why] DVI is TMDS signal like HDMI but without audio. Current signal check does not correctly reflect DVI clock programming. [How] Define a new signal check for TMDS that includes DVI to HDMI TMDS programming. Reviewed-by:
-
Alex Hung authored
The comparisons intend to be DCN401 inclusive, and fix it by adding equal signs. Reviewed-by:
-
Wenjing Liu authored
The functions are missing. These two functions are required to support MST. Reviewed-by:
-
Rodrigo Siqueira authored
The function that commits planes calls the same set of functions twice, and in the case of the FAMs utilization, it is not desired to call the dmub, hwss_build and hwss_execute. This commit just removes the unnecessary calls to those functions. Acked-by:
-
Wenjing Liu authored
Move dsc functions from dc.c to dc_dsc.c. Co-developed-by:
-
- 17 May, 2024 17 commits
-
-
Yang Wang authored
fix ACA no query result after gpu reset. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
-
Lijo Lazar authored
Replace the legacy interface with amdgpu_dpm_set_pm_policy to set XGMI PLPD mode. Also, xgmi_plpd_policy sysfs node is not used by any client. Remove that as well. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Acked-by:
-
Lijo Lazar authored
On arcturus, allow changing xgmi plpd policy through 'pm_policy/xgmi_plpd' sysfs interface. Signed-off-by:
-
Yang Wang authored
modify the lock type to 'spinlock' to avoid schedule issue in interrupt context. Signed-off-by:
-
Lijo Lazar authored
On aldebaran, allow changing xgmi plpd policy through 'pm_policy/xgmi_plpd' sysfs interface. Signed-off-by:
-
Lijo Lazar authored
On SOCs with SMU v13.0.6, allow changing xgmi plpd policy through 'pm_policy/xgmi_plpd' sysfs interface. Signed-off-by:
-
Lijo Lazar authored
Add support to set XGMI PLPD policy levels through 'pm_policy/xgmi_plpd' sysfs node. Signed-off-by:
-
Lijo Lazar authored
Add support to select pstate policy in SOCs with SMUv13.0.6 Signed-off-by:
-
Lijo Lazar authored
Add PMF message to select a Pstate policy in SOCs with SMU v13.0.6. Signed-off-by:
-
Lijo Lazar authored
Add support to set/get information about different DPM policies. The support is only available on SOCs which use swsmu architecture. A DPM policy type may be defined with different levels. For example, a policy may be defined to select Pstate preference and then later a pstate preference may be chosen. Signed-off-by:
-
Yang Wang authored
modify the lock type to 'spinlock' to avoid schedule issue in interrupt context. Signed-off-by:
-
Tvrtko Ursulin authored
Accurately show all placements when describing objects in debugfs, instead of bunching them up under the 'CPU' placement. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Cc: Christian König <christian.koenig@amd.com> Cc: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
-
Tvrtko Ursulin authored
All apart from AMDGPU_GEM_DOMAIN_GTT memory domains map 1:1 to TTM placements. And the former be either AMDGPU_PL_PREEMPT or TTM_PL_TT, depending on AMDGPU_GEM_CREATE_PREEMPTIBLE. Simplify a few places in the code which convert the TTM placement into a domain by checking against the current placement directly. In the conversion AMDGPU_PL_PREEMPT either does not have to be handled because amdgpu_mem_type_to_domain() cannot return that value anyway. v2: * Remove AMDGPU_PL_PREEMPT handling. v3: * Rebase. Signed-off-by:
-
Tvrtko Ursulin authored
Help code readability by replacing a bunch of: bo->tbo.base.resv == vm->root.bo->tbo.base.resv With: amdgpu_vm_is_bo_always_valid(vm, bo) No functional changes. v2: * Rename helper and move to amdgpu_vm. (Christian) v3: * Use Christian's kerneldoc. v4: * Fixed logic inversion in amdgpu_vm_bo_get_memory. Signed-off-by:
-
Srinivasan Shanmugam authored
This commit removes a duplicate check for *is_queue_unmap in the sdma_v7_0_ring_set_wptr function. The check at line 171 was considered dead code because at this point in the code, we already know that *is_queue_unmap is false due to the check at line 161. By removing this unnecessary check, improves the readability of the code Fixes the below: drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c:171 sdma_v7_0_ring_set_wptr() warn: duplicate check '*is_queue_unmap' (previous on line 161) drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c 140 static void sdma_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 141 { 142 struct amdgpu_device *adev = ring->adev; 143 uint32_t *wptr_saved; 144 uint32_t *is_queue_unmap; 145 uint64_t aggregated_db_index; 146 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size; 147 148 DRM_DEBUG("Setting write pointer\n"); 149 150 if (ring->is_mes_queue) { 151 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 152 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + ^^^^^^^^^^^^^^^^ Set here 153 sizeof(uint32_t)); 154 aggregated_db_index = 155 amdgpu_mes_get_aggregated_doorbell_index(adev, 156 ring->hw_prio); 157 158 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 159 ring->wptr << 2); 160 *wptr_saved = ring->wptr << 2; 161 if (*is_queue_unmap) { ^^^^^^^^^^^^^^^ Checked here 162 WDOORBELL64(aggregated_db_index, ring->wptr << 2); 163 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 164 ring->doorbell_index, ring->wptr << 2); 165 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 166 } else { 167 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 168 ring->doorbell_index, ring->wptr << 2); 169 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 170 --> 171 if (*is_queue_unmap) ^^^^^^^^^^^^^^^ This is dead code. We know it's false. 172 WDOORBELL64(aggregated_db_index, 173 ring->wptr << 2); 174 } 175 } else { 176 if (ring->use_doorbell) { 177 DRM_DEBUG("Using doorbell -- " 178 "wptr_offs == 0x%08x " Fixes: b412351e ("drm/amdgpu: Add sdma v7_0 ip block support (v7)") Cc: Likun Gao <Likun.Gao@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reported-by:Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
-
Tim Van Patten authored
The following commit updated gmc->noretry from 0 to 1 for GC HW IP 9.3.0: commit 5f3854f1 ("drm/amdgpu: add more cases to noretry=1") This causes the device to hang when a page fault occurs, until the device is rebooted. Instead, revert back to gmc->noretry=0 so the device is still responsive. Fixes: 5f3854f1 ("drm/amdgpu: add more cases to noretry=1") Signed-off-by:Tim Van Patten <timvp@google.com> Signed-off-by:
-
Ruijing Dong authored
Update the capabilities for supporting 8k encoding. Reviewed-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Acked-by:
Ruijing Dong <ruijing.dong@amd.com> Signed-off-by:
-
