- 02 Jul, 2016 7 commits
-
-
Dong Aisheng authored
On Freescale i.MX7D platform, all clocks operations, including enable/disable, rate change and re-parent, requires its parent clock on. Current clock core can not support it well. This patch adding flag CLK_OPS_PARENT_ENABLE to handle this special case in clock core that enable its parent clock firstly for each operation and disable it later after operation complete. The patch part 2 fixes set clock rate and set parent while its parent is off. The most special case is for set_parent() operation which requires all parents including both old and new one to be enabled at the same time during the operation. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> [sboyd@codeaurora.org: Move set_rate tracepoint after prepare_enable] Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
-
Dong Aisheng authored
On Freescale i.MX7D platform, all clocks operations, including enable/disable, rate change and re-parent, requires its parent clock enable. Current clock core can not support it well. This patch introduce a new flag CLK_OPS_PARENT_ENABLE to handle this special case in clock core that enable its parent clock firstly for each operation and disable it later after operation complete. The patch part 1 fixes the possible disabling clocks while its parent is off during kernel booting phase in clk_disable_unused_subtree(). Before the completion of kernel booting, clock tree is still not built completely, there may be a case that the child clock is on but its parent is off which could be caused by either HW initial reset state or bootloader initialization. Taking bootloader as an example, we may enable all clocks in HW by default. And during kernel booting time, the parent clock could be disabled in its driver probe due to calling clk_prepare_enable and clk_disable_unprepare. Because it's child clock is only enabled in HW while its SW usecount in clock tree is still 0, so clk_disable of parent clock will gate the parent clock in both HW and SW usecount ultimately. Then there will be a child clock is still on in HW but its parent is already off. Later in clk_disable_unused(), this clock disable accessing while its parent off will cause system hang due to the limitation of HW which must require its parent on. This patch simply enables the parent clock first before disabling if flag CLK_OPS_PARENT_ENABLE is set in clk_disable_unused_subtree(). This is a simple solution and only affects booting time. After kernel booting up the clock tree is already created, there will be no case that child is off but its parent is off. So no need do this checking for normal clk_disable() later. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by:
-
Dong Aisheng authored
No function level change, just moving code place. clk_disable_unused function will need to call clk_core_prepare_enable/ clk_core_disable_unprepare when adding CLK_OPS_PARENT_ENABLE features. So move it after clk_core_disable_unprepare to avoid adding forward declared functions later. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by:
-
Dong Aisheng authored
This can be useful when clock core wants to enable/disable clocks. Then we don't have to convert the struct clk_core to struct clk to call clk_enable/clk_disable which is a bit un-align with exist using. And after introduce clk_core_{enable|disable}_lock, we can refine clk_enable and clk_disable a bit. As well as clk_core_{enable|disable}_lock, we also added clk_core_{prepare|unprepare}_lock and clk_core_prepare_enable/ clk_core_unprepare_disable for clock core to easily use. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: -
Stephen Boyd authored
Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: Placeholder for the rk3399 watchdog pclk, some newly exported rk3228 clockids and a small fix for the not yet used spdif to displayport clock on the rk3399. * tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits clk: rockchip: export rk3228 MAC clocks clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk clk: rockchip: export rk3228 audio clocks clk: rockchip: include rk3228 downstream muxes into fractional dividers clk: rockchip: fix incorrect rk3228 clock registers clk: rockchip: add clock-ids for rk3228 MAC clocks clk: rockchip: add clock-ids for rk3228 audio clocks clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
-
Stephen Boyd authored
Merge tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk driver updates from Thierry Reding: Fixes and enhancements mostly for Tegra210 clocks that allow DSI and HDMI to work on Tegra X1. There's also a refactoring, including fixes, the USB PLL. * tag 'tegra-for-4.8-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Initialize UTMI PLL when enabling PLLU clk: tegra: Micro-optimize Tegra210 clock setup clk: tegra: Make sor_safe the parent of dpaux and dpaux1 clk: tegra: Mark timer clock as critical clk: tegra: Enable sor1 and sor1_src on Tegra210 clk: tegra: Squash sor1 safe/brick/src into a single mux clk: tegra: Disable spread spectrum on pll_d2 clk: tegra: Fixup post dividers on Tegra210
-
Maxime Ripard authored
The only way for a fixed factor clock to change its rate would be to change its parent rate. Since passing blindly CLK_SET_RATE_PARENT might break a lot of platforms that were relying on the fact that the parent rate wouldn't change, introduce a compatible-based whitelist that will allow clocks to opt-in that flag. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
-
- 30 Jun, 2016 27 commits
-
-
Xing Zheng authored
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx, it should be bit_8, let's fix it. Fixes: 11551005 ("clk: rockchip: add clock controller for the RK3399") Reported-by:
Chris Zhong <zyw@rock-chips.com> Tested-by:
Xing Zheng <zhengxing@rock-chips.com> Cc: stable@vger.kernel.org Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
-
Xing Zheng authored
This patch exports related MAC clocks for dts reference. Signed-off-by:
-
Xing Zheng authored
The sclk_macphy_50m is confusing, the sclk_mac_extclk describes a external clock clearly. Signed-off-by:
-
Xing Zheng authored
This patch exports related i2s/spdif clocks for dts reference. Signed-off-by:
-
Heiko Stuebner authored
-
Xing Zheng authored
During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3228 clocks were left out, so convert them now. Signed-off-by:
-
Stephen Boyd authored
Merge tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX clk driver updates from Shawn Guo: - A few correction and improvements on pllv3 driver around AV pll clock rate calculation, parent setting and power bit handling - Correct i.MX6UL GPT2 clock names - A couple of minor fixes on i.MX7D clock driver on DRAM clocks * tag 'imx-clk-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx6ul: fix gpt2 clock names clk: imx: refine the powerdown bit of clk-pllv3 clk: imx: clk-pllv3: fix incorrect handle of enet powerdown bit clk: imx: fix pll clock parents clk: imx7d: correct dram pll type clk: imx7d: correct dram root clk parent select clk: imx: correct AV PLL rate formula
-
Stephen Boyd authored
* clk-hw-unregister-fixed-rate: clk: fixed-rate: add clk_hw_unregister_fixed_rate()
-
Masahiro Yamada authored
This will be used to migrate to the clk_hw APIs. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
-
Jiancheng Xue authored
1. Add driver remove path. 2. Fix some issues. -Fix the ordering issue about clock provider being published. -Add error checking upon registering clocks. Signed-off-by:
Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by:
-
Jiancheng Xue authored
Add hisi_clk_unregister_* functions. Signed-off-by:
-
Jiancheng Xue authored
Add error processing for hisi_clk_register_* functions. Signed-off-by:
-
Jiancheng Xue authored
Before, there was an ordering issue that the clock provider had been published in hisi_clk_init before it could provide valid clocks to consumers. hisi_clk_alloc is just used to allocate memory space for struct hisi_clock_data. It makes it possible to publish the provider after the clocks are ready. Signed-off-by:
-
Jiancheng Xue authored
Change the input arguments type to struct platform_device pointer. Signed-off-by:
-
Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by:
Stephen Boyd <stephen.boyd@linaro.org> Acked-by:
Andi Shyti <andi.shyti@samsung.com> Reviewed-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by:
-
Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by:
-
Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Jon Mason <jonmason@broadcom.com> Cc: Simran Rai <ssimran@broadcom.com> Signed-off-by:
Ray Jui <rjui@broadcom.com> Signed-off-by:
-
Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
-
Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by:
-
Stephen Boyd authored
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by:
-
Stephen Boyd authored
* clk-st-critical: clk: st: clkgen-pll: Detect critical clocks clk: st: clkgen-fsyn: Detect critical clocks clk: st: clk-flexgen: Detect critical clocks
-
Lee Jones authored
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
-
Lee Jones authored
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. Clocks are marked as CRITICAL using clk flags. This patch also ensures flags are peculated through the framework in the correct manner. Signed-off-by:
-
Lee Jones authored
Utilise the new Critical Clock infrastructure to mark clocks which much not be disabled as CRITICAL. While we're at it, reduce the coverage of the flex_flags variable, since it's only really used in a single for() loop. Signed-off-by:
-
Stephen Boyd authored
* clk-hi6220-rtc: clk: hi6220: Add RTC clock for pl031
-
Zhangfei Gao authored
Adds clk support for the pl031 RTC on hi6220 Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> [jstultz: Forward ported, tweaked commit description] Signed-off-by:
John Stultz <john.stultz@linaro.org> Signed-off-by:
-
Andrew Bresticker authored
Move the UTMI PLL initialization code form clk-tegra<chip>.c files into clk-pll.c. UTMI PLL was being configured and set in HW control right after registration. However, when the clock init_table is processed and child clks of PLLU are enabled, it will call in and enable PLLU as well, and initiate SW enabling sequence even though PLLU is already in HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. Doing the initialization once during pllu_enable means we configure it properly into HW control. A side effect of the commonization/localization of the UTMI PLL init code, is that it corrects some errors that were present for earlier generations. For instance, in clk-tegra124.c, it used to have: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) when the correct shift to use is present in the new version: #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) which matches the Tegra124 TRM register definition. Signed-off-by:Andrew Bresticker <abrestic@chromium.org> [rklein: Merged in some later fixes for potential deadlocks] Signed-off-by:
Rhyland Klein <rklein@nvidia.com> [treding: coding style bike-shedding, remove unused variable] Signed-off-by:
Thierry Reding <treding@nvidia.com>
-
- 29 Jun, 2016 3 commits
-
-
Stephen Boyd authored
* clk-notify: clk: Provide notifier stubs when !COMMON_CLK
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull second batch of Renesas clk driver updates from Geert Uytterhoeven: - Add support for R-Car V2H, - Add FDP1, DRIF, and thermal clocks on R-Car H3, - Correct a wrong parent clock. * tag 'clk-renesas-for-v4.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7795: Add THS/TSC clock clk: renesas: r8a7795: Add DRIF clock clk: renesas: r8a7795: Correct lvds clock parent clk: renesas: r8a7795: Provide FDP1 clocks clk: renesas: Add R8A7792 support clk: renesas: mstp: Document R8A7792 support clk: renesas: rcar-gen2: Document R8A7792 support
-
Krzysztof Kozlowski authored
The clk notifier symbols are hidden by COMMON_CLK. However on some platforms HAVE_CLK might be set while COMMON_CLK not which leads to compile test build errors like: $ make.cross ARCH=sh drivers/devfreq/tegra-devfreq.c: In function 'tegra_actmon_rate_notify_cb': >> drivers/devfreq/tegra-devfreq.c:391:16: error: 'POST_RATE_CHANGE' undeclared (first use in this function) if (action != POST_RATE_CHANGE) ^ drivers/devfreq/tegra-devfreq.c: In function 'tegra_devfreq_probe': >> drivers/devfreq/tegra-devfreq.c:654:8: error: implicit declaration of function 'clk_notifier_register' [-Werror=implicit-function-declaration] err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb); ^ Export the macros and data type declarations outside of COMMON_CLK ifdef and provide stubs to fix the compile testing. Reported-by:kbuild test robot <lkp@intel.com> Signed-off-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
-
- 28 Jun, 2016 2 commits
-
-
Stephen Boyd authored
Merge tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull support for Renesas R-car M3-W from Geert Uytterhoeven: Add initial support for the Clock Pulse Generator and Module Standby and Software Reset modules on the Renesas R-Car M3-W SoC: - Basic core clocks, - SCIF2 (console) module clock, - INTC-AP (GIC) module clock. * tag 'clk-renesas-for-v4.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: cpg-mssr: Add support for R-Car M3-W clk: renesas: cpg-mssr: Extract common R-Car Gen3 support code clk: renesas: Add r8a7796 CPG Core Clock Definitions clk: renesas: cpg-mssr: Document r8a7796 support
-
Stephen Boyd authored
This clk is critical to operation of the SoC and should never be turned off. Furthermore, there are no consumers of this clk so let's just delete it so things like eMMC work. Reported-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver") Signed-off-by:
-
- 23 Jun, 2016 1 commit
-
-
Thierry Reding authored
sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only natural, but also slightly more efficient, to initialize it before its children. This avoids orphaning the dpaux and dpaux1 clocks only to get them reparented when the sor_safe clock is registered. Acked-by:
Jon Hunter <jonathanh@nvidia.com> Tested-by:
-
