- 28 Sep, 2017 5 commits
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Dave Airlie authored
If we bump this up a level, we can ask about it, for now, just default to what amdgpu does. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Andres Rodriguez authored
This patch provides a guarantee that the first n queues allocated by an application will be on different pipes. Where n is the number of pipes available from the hardware. This helps avoid ring aliasing which can result in work executing in time-sliced mode instead of truly parallel mode. Reviewed-by:
Andres Rodriguez <andresx7@gmail.com> Signed-off-by:
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Andres Rodriguez authored
Useful for testing the effects of multipipe compute without recompiling. Acked-by:
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Andres Rodriguez authored
A performance regression for OpenCL tests on Polaris11 had this feature disabled for all asics. Instead, disable it selectively on the affected asics. Acked-by:
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Alex Deucher authored
The error handling for virtual functions assumed a single vf per VM and didn't properly account for bare metal. Make the error arrays per device and add locking. Reviewed-by:
Gavin Wan <gavin.wan@amd.com> Signed-off-by:
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- 26 Sep, 2017 35 commits
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Alex Deucher authored
It was not clear. The rest of the driver is MIT/X11. Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Samuel Li authored
v2: drop hdp invalidate/flush. v3: honor pgoff during prime mmap. Add a barrier after cpu access. v4: drop begin/end_cpu_access() for now, revisit later. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Reviewed-by:
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Rex Zhu authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h use PHM_WAIT_INDIRECT_FIELD instand. Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
the macro is as same as PHM_WRITE_FIELD Reviewed-by:
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Rex Zhu authored
the macro is as same as PHM_WRITE_INDIRECT_FIELD Reviewed-by:
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Rex Zhu authored
the macro is not relevant to SMU, so rename SMU_WAIT_FIELD_UNEQUAL to PHM_WAIT_FIELD_UNEQUAL and move to hwmgr.h Reviewed-by:
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Rex Zhu authored
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD Reviewed-by:
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Rex Zhu authored
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL Reviewed-by:
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Rex Zhu authored
the macro is not relevent to SMU, so move to hwmgr.h and rename to PHM_WAIT_INDIRECT_FIELD_UNEQUAL Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
in VFPF macros to support virtualization Reviewed-by:
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Rex Zhu authored
delete struct smumgr, put smu backend function table in struct hwmgr Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
unify to use struct hwmgr as function parameter in smumgr. Reviewed-by:
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Christian König authored
Just set the CPU access required flag when we pin it. Signed-off-by:
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Monk Liu authored
this fix memory leak due to request_firmware after driver unloaded v2: release gmc firmware for gmc6/7/8 as well Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
fix missing finish uvd enc_ring. v2: since the adev pointer check in already in ring_fini so drop the check outsider Signed-off-by:
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Monk Liu authored
this way after KIQ MQD released in drv unloading, CPC can still let KIQ access this MQD thus RLCV SAVE_VF will not fail v2: always use VRAM domain for KIQ MQD no matter BM or SRIOV Signed-off-by:
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Monk Liu authored
v2: move kcq_disable out of SRIOV, make it genearal Signed-off-by:
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Monk Liu authored
only with this way we can debug the VMC page fault issue Signed-off-by:
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Yong Zhao authored
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
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Yong Zhao authored
When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by:
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Yong Zhao authored
Signed-off-by:
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Christian König authored
Use 2MB fragment size by default for older hardware generations as well. Signed-off-by:
John Bridgman <john.bridgman@amd.com> Reviewed-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Xiangliang.Yu authored
SRIOV doesn't implement PMC capability of PCIe, so it can't update power state by reading PMC register. Currently, amdgpu driver doesn't disable pci device when removing driver, the enable_cnt of pci device will not be decrease to 0. When reloading driver, pci_enable_device will do nothing as enable_cnt is not zero. And power state will not be updated as PMC is not support. So current_state of pci device is not D0 state and pci_enable_msi return fail. Add pci_disable_device when remmoving driver to fix the issue. Signed-off-by:
Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by:
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Rex Zhu authored
currently, not all asics implement this callback function so not return error to avoid powerplay initialize failed in those asices Reviewed-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
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Eric Huang authored
Change to more meaningful range that triggers thermal interrupts. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by:
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Eric Huang authored
Signed-off-by:
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