/*
 * Copyright (C) 2019  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _clk_10_0_2_OFFSET_HEADER
#define _clk_10_0_2_OFFSET_HEADER



// addressBlock: clk_clk1_0_SmuClkDec
// base address: 0x5b800
#define mmCLK1_CLK_PLL_REQ                                                                             0x000f
#define mmCLK1_CLK_PLL_REQ_BASE_IDX                                                                    1
#define mmCLK1_CLK0_BYPASS_CNTL                                                                        0x0049
#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                               1
#define mmCLK1_CLK1_BYPASS_CNTL                                                                        0x0053
#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                               1
#define mmCLK1_CLK2_BYPASS_CNTL                                                                        0x005d
#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                               1
#define mmCLK1_CLK2_STATUS                                                                             0x005e
#define mmCLK1_CLK2_STATUS_BASE_IDX                                                                    1
#define mmCLK1_CLK3_DFS_CNTL                                                                           0x005f
#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX                                                                  1
#define mmCLK1_CLK3_DS_CNTL                                                                            0x0060
#define mmCLK1_CLK3_DS_CNTL_BASE_IDX                                                                   1
#define mmCLK1_CLK3_ALLOW_DS                                                                           0x0061
#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX                                                                  1
#define mmCLK1_CLK3_BYPASS_CNTL                                                                        0x0067
#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                               1
#define mmCLK1_CLK0_CURRENT_CNT                                                                        0x008a
#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX                                                               1
#define mmCLK1_CLK1_CURRENT_CNT                                                                        0x008b
#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX                                                               1
#define mmCLK1_CLK2_CURRENT_CNT                                                                        0x008c
#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX                                                               1
#define mmCLK1_CLK3_CURRENT_CNT                                                                        0x008d
#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX                                                               1


#endif
