* MTK MMC controller

The MTK  MSDC can act as a MMC controller
to support MMC, SD, and SDIO types of memory cards.

This file documents differences between the core properties in mmc.txt
and the properties used by the msdc driver.

Required properties:
- compatible: value should be either of the following.
	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
	"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC

- reg: physical base address of the controller and length
- interrupts: Should contain MSDC interrupt number
- clocks: Should contain phandle for the clock feeding the MMC controller
- clock-names: Should contain the following:
	"source" - source clock (required)
	"hclk" - HCLK which used for host (required)
	"source_cg" - independent source clock gate (required for MT2712)
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl
- vmmc-supply: power to the Core
- vqmmc-supply: power to the IO

Optional properties:
- assigned-clocks: PLL of the source clock
- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
- hs400-ds-delay: HS400 DS delay setting
- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
				This field has total 32 stages.
				The value is an integer from 0 to 31.
- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
				This field has total 32 stages.
				The value is an integer from 0 to 31.
- mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection
				       If present,HS400 command responses are sampled on rising edges.
				       If not present,HS400 command responses are sampled on falling edges.
- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
		     error caused by stop clock(fifo full)
		     Valid range = [0:0x7]. if not present, default value is 0.
		     applied to compatible "mediatek,mt2701-mmc".

Examples:
mmc0: mmc@11230000 {
	compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
	reg = <0 0x11230000 0 0x108>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
	vmmc-supply = <&mt6397_vemc_3v3_reg>;
	vqmmc-supply = <&mt6397_vio18_reg>;
	clocks = <&pericfg CLK_PERI_MSDC30_0>,
	         <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
	clock-names = "source", "hclk";
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
	hs400-ds-delay = <0x14015>;
	mediatek,hs200-cmd-int-delay = <26>;
	mediatek,hs400-cmd-int-delay = <14>;
	mediatek,hs400-cmd-resp-sel-rising;
};
