Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs

The bindings follow the mmc[1], clock[2] and interrupt[3] bindings.
Only deviations are documented here.

  [1] Documentation/devicetree/bindings/mmc/mmc.txt
  [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
  [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt

Required Properties:
	- compatible: should be one of:
			"ti,am654-sdhci-5.1": SDHCI on AM654 device.
			"ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.
			"ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.
	- reg: Must be two entries.
		- The first should be the sdhci register space
		- The second should the subsystem/phy register space
	- clocks: Handles to the clock inputs.
	- clock-names: Tuple including "clk_xin" and "clk_ahb"
	- interrupts: Interrupt specifiers
	Output tap delay for each speed mode:
	- ti,otap-del-sel-legacy
	- ti,otap-del-sel-mmc-hs
	- ti,otap-del-sel-sd-hs
	- ti,otap-del-sel-sdr12
	- ti,otap-del-sel-sdr25
	- ti,otap-del-sel-sdr50
	- ti,otap-del-sel-sdr104
	- ti,otap-del-sel-ddr50
	- ti,otap-del-sel-ddr52
	- ti,otap-del-sel-hs200
	- ti,otap-del-sel-hs400
	  These bindings must be provided otherwise the driver will disable the
	  corresponding speed mode (i.e. all nodes must provide at least -legacy)

Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit):
	- ti,trm-icp: DLL trim select
	- ti,driver-strength-ohm: driver strength in ohms.
				  Valid values are 33, 40, 50, 66 and 100 ohms.
Optional Properties:
	- ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0.

Example:

	sdhci0: sdhci@4f80000 {
		compatible = "ti,am654-sdhci-5.1";
		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
		power-domains = <&k3_pds 47>;
		clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
		clock-names = "clk_ahb", "clk_xin";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		sdhci-caps-mask = <0x80000007 0x0>;
		mmc-ddr-1_8v;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x5>;
		ti,otap-del-sel-hs400 = <0x0>;
		ti,trm-icp = <0x8>;
	};
