Qualcomm adreno/snapdragon GPU

Required properties:
- compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
	      "amd,imageon-XYZ.W", "amd,imageon"
    for example: "qcom,adreno-306.0", "qcom,adreno"
  Note that you need to list the less specific "qcom,adreno" (since this
  is what the device is matched on), in addition to the more specific
  with the chip-id.
  If "amd,imageon" is used, there should be no top level msm device.
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the gpu.
- clocks: device clocks (if applicable)
  See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required by a3xx, a4xx and a5xx
  cores:
  * "core"
  * "iface"
  * "mem_iface"
  For GMU attached devices the GPU clocks are not used and are not required. The
  following devices should not list clocks:
   - qcom,adreno-630.2
- iommus: optional phandle to an adreno iommu instance
- operating-points-v2: optional phandle to the OPP operating points
- interconnects: optional phandle to an interconnect provider.  See
  ../interconnect/interconnect.txt for details. Some A3xx and all A4xx platforms
  will have two paths; all others will have one path.
- interconnect-names: The names of the interconnect paths that correspond to the
  interconnects property. Values must be gfx-mem and ocmem.
- qcom,gmu: For GMU attached devices a phandle to the GMU device that will
  control the power for the GPU. Applicable targets:
    - qcom,adreno-630.2
- zap-shader: For a5xx and a6xx devices this node contains a memory-region that
  points to reserved memory to store the zap shader that can be used to help
  bring the GPU out of secure mode.
- firmware-name: optional property of the 'zap-shader' node, listing the
  relative path of the device specific zap firmware.
- sram: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
        a4xx Snapdragon SoCs. See
        Documentation/devicetree/bindings/sram/qcom,ocmem.yaml.

Example 3xx/4xx:

/ {
	...

	gpu: adreno@fdb00000 {
		compatible = "qcom,adreno-330.2",
		             "qcom,adreno";
		reg = <0xfdb00000 0x10000>;
		reg-names = "kgsl_3d0_reg_memory";
		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_3d0_irq";
		clock-names = "core",
		              "iface",
		              "mem_iface";
		clocks = <&mmcc OXILI_GFX3D_CLK>,
		         <&mmcc OXILICX_AHB_CLK>,
		         <&mmcc OXILICX_AXI_CLK>;
		sram = <&gpu_sram>;
		power-domains = <&mmcc OXILICX_GDSC>;
		operating-points-v2 = <&gpu_opp_table>;
		iommus = <&gpu_iommu 0>;
	};

	gpu_sram: ocmem@fdd00000 {
		compatible = "qcom,msm8974-ocmem";

		reg = <0xfdd00000 0x2000>,
		      <0xfec00000 0x180000>;
		reg-names = "ctrl",
		            "mem";

		clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
		         <&mmcc OCMEMCX_OCMEMNOC_CLK>;
		clock-names = "core",
		              "iface";

		#address-cells = <1>;
		#size-cells = <1>;

		gpu_sram: gpu-sram@0 {
			reg = <0x0 0x100000>;
			ranges = <0 0 0xfec00000 0x100000>;
		};
	};
};

Example a6xx (with GMU):

/ {
	...

	gpu@5000000 {
		compatible = "qcom,adreno-630.2", "qcom,adreno";
		#stream-id-cells = <16>;

		reg = <0x5000000 0x40000>, <0x509e000 0x10>;
		reg-names = "kgsl_3d0_reg_memory", "cx_mem";

		/*
		 * Look ma, no clocks! The GPU clocks and power are
		 * controlled entirely by the GMU
		 */

		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

		iommus = <&adreno_smmu 0>;

		operating-points-v2 = <&gpu_opp_table>;

		interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
		interconnect-names = "gfx-mem";

		qcom,gmu = <&gmu>;

		zap-shader {
			memory-region = <&zap_shader_region>;
			firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"
		};
	};
};
