Microchip Ocelot switch driver family
=====================================

Felix
-----

The VSC9959 core is currently the only switch supported by the driver, and is
found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root
complex. As a result, the ethernet-switch node is a sub-node of the PCIe root
complex node and its "reg" property conforms to the parent node bindings:

* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
  in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).

It does not require a "compatible" string.

The interrupt line is used to signal availability of PTP TX timestamps and for
TSN frame preemption.

For the external switch ports, depending on board configuration, "phy-mode" and
"phy-handle" are populated by board specific device tree instances. Ports 4 and
5 are fixed as internal ports in the NXP LS1028A instantiation.

The CPU port property ("ethernet") configures the feature called "NPI port" in
the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal
2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
use case.  Moving the NPI port to an external switch port is hardware possible,
but there is no platform support for the Linux system on the LS1028A chip to
operate as an entire slave DSA chip.  NPI functionality (and therefore DSA
tagging) is supported on a single port at a time.

Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled
by default, and should be enabled on a per-board basis). But if any external
switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as
well, regardless of whether it is configured as the DSA master or not. This is
because the Felix PHYLINK implementation accesses the MAC PCS registers, which
in hardware truly belong to the ENETC port #2 and not to Felix.

Supported PHY interface types (appropriate SerDes protocol setting changes are
needed in the RCW binary):

* phy_mode = "internal": on ports 4 and 5
* phy_mode = "sgmii": on ports 0, 1, 2, 3
* phy_mode = "qsgmii": on ports 0, 1, 2, 3
* phy_mode = "usxgmii": on ports 0, 1, 2, 3
* phy_mode = "2500base-x": on ports 0, 1, 2, 3

For the rest of the device tree binding definitions, which are standard DSA and
PCI, refer to the following documents:

Documentation/devicetree/bindings/net/dsa/dsa.txt
Documentation/devicetree/bindings/pci/pci.txt

Example:

&soc {
	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
		ethernet-switch@0,5 {
			reg = <0x000500 0 0 0 0>;
			/* IEP INT_B */
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/* External ports */
				port@0 {
					reg = <0>;
					label = "swp0";
				};

				port@1 {
					reg = <1>;
					label = "swp1";
				};

				port@2 {
					reg = <2>;
					label = "swp2";
				};

				port@3 {
					reg = <3>;
					label = "swp3";
				};

				/* Tagging CPU port */
				port@4 {
					reg = <4>;
					ethernet = <&enetc_port2>;
					phy-mode = "internal";

					fixed-link {
						speed = <2500>;
						full-duplex;
					};
				};

				/* Non-tagging CPU port */
				port@5 {
					reg = <5>;
					phy-mode = "internal";
					status = "disabled";

					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};
	};
};
