• Cyril Bur's avatar
    powerpc: tm: Enable transactional memory (TM) lazily for userspace · 5d176f75
    Cyril Bur authored
    Currently the MSR TM bit is always set if the hardware is TM capable.
    This adds extra overhead as it means the TM SPRS (TFHAR, TEXASR and
    TFAIR) must be swapped for each process regardless of if they use TM.
    
    For processes that don't use TM the TM MSR bit can be turned off
    allowing the kernel to avoid the expensive swap of the TM registers.
    
    A TM unavailable exception will occur if a thread does use TM and the
    kernel will enable MSR_TM and leave it so for some time afterwards.
    Signed-off-by: default avatarCyril Bur <cyrilbur@gmail.com>
    Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
    5d176f75
processor.h 14 KB