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Tejun Heo authored
This timeout was set low because previously PMP register access was done via polling and register access timeouts could stack up. This is no longer the case. One timeout will make all following accesses fail immediately. In rare cases both marvell and SIMG PMPs need almost a second. Bump it to 3s. While at it, rename it to SATA_PMP_RW_TIMEOUT. It's not specific to SCR access. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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