Mark some additional registers as volatile. The write sequencer control
registers should not be cached, as we don't ever want their value
synchronised as this might cause a write sequence to be accidentally
initiated.

Additionally, the DAC_COMP registers require special preconditions to
write so there values wouldn't be updated accurately during a register
sync.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>