Commit 0031fb96 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin

drm/i915: Assorted dev_priv cleanups

A small selection of macros which can only accept dev_priv from
now on and a resulting trickle of fixups.
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
parent b42fe9ca
...@@ -2527,28 +2527,31 @@ struct drm_i915_cmd_table { ...@@ -2527,28 +2527,31 @@ struct drm_i915_cmd_table {
#define ALL_ENGINES (~0) #define ALL_ENGINES (~0)
#define HAS_ENGINE(dev_priv, id) \ #define HAS_ENGINE(dev_priv, id) \
(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id))) (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop) #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
#define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts) #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts)
#define USES_PPGTT(dev) (i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) #define HAS_HW_CONTEXTS(dev_priv) ((dev_priv)->info.has_hw_contexts)
#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv) (i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3)
#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
((dev_priv)->info.overlay_needs_physical)
/* Early gen2 have a totally busted CS tlb and require pinned batches. */ /* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv)) #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_845G(dev_priv))
...@@ -2565,8 +2568,8 @@ struct drm_i915_cmd_table { ...@@ -2565,8 +2568,8 @@ struct drm_i915_cmd_table {
* legacy irq no. is shared with another device. The kernel then disables that * legacy irq no. is shared with another device. The kernel then disables that
* interrupt source and so prevents the other device from working properly. * interrupt source and so prevents the other device from working properly.
*/ */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq) #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming. * rows, which changed the alignment requirements and fence programming.
......
...@@ -48,7 +48,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o ...@@ -48,7 +48,7 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
static bool cpu_cache_is_coherent(struct drm_device *dev, static bool cpu_cache_is_coherent(struct drm_device *dev,
enum i915_cache_level level) enum i915_cache_level level)
{ {
return HAS_LLC(dev) || level != I915_CACHE_NONE; return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE;
} }
static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
...@@ -1757,7 +1757,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) ...@@ -1757,7 +1757,7 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
goto err_rpm; goto err_rpm;
/* Access to snoopable pages through the GTT is incoherent. */ /* Access to snoopable pages through the GTT is incoherent. */
if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) {
ret = -EFAULT; ret = -EFAULT;
goto err_unlock; goto err_unlock;
} }
...@@ -3180,7 +3180,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, ...@@ -3180,7 +3180,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
if (ret) if (ret)
return ret; return ret;
if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { if (!HAS_LLC(to_i915(obj->base.dev)) &&
cache_level != I915_CACHE_NONE) {
/* Access to snoopable pages through the GTT is /* Access to snoopable pages through the GTT is
* incoherent and on some machines causes a hard * incoherent and on some machines causes a hard
* lockup. Relinquish the CPU mmaping to force * lockup. Relinquish the CPU mmaping to force
...@@ -3884,7 +3885,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size) ...@@ -3884,7 +3885,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size)
obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.write_domain = I915_GEM_DOMAIN_CPU;
obj->base.read_domains = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU;
if (HAS_LLC(dev)) { if (HAS_LLC(dev_priv)) {
/* On some devices, we can have the GPU use the LLC (the CPU /* On some devices, we can have the GPU use the LLC (the CPU
* cache) for about a 10% performance improvement * cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than * compared to uncached. Graphics requests other than
...@@ -4130,7 +4131,7 @@ int i915_gem_suspend(struct drm_device *dev) ...@@ -4130,7 +4131,7 @@ int i915_gem_suspend(struct drm_device *dev)
* machines is a good idea, we don't - just in case it leaves the * machines is a good idea, we don't - just in case it leaves the
* machine in an unusable condition. * machine in an unusable condition.
*/ */
if (HAS_HW_CONTEXTS(dev)) { if (HAS_HW_CONTEXTS(dev_priv)) {
int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
WARN_ON(reset && reset != -ENODEV); WARN_ON(reset && reset != -ENODEV);
} }
...@@ -4223,7 +4224,7 @@ i915_gem_init_hw(struct drm_device *dev) ...@@ -4223,7 +4224,7 @@ i915_gem_init_hw(struct drm_device *dev)
/* Double layer security blanket, see i915_gem_init() */ /* Double layer security blanket, see i915_gem_init() */
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9)
I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
if (IS_HASWELL(dev_priv)) if (IS_HASWELL(dev_priv))
......
...@@ -287,7 +287,7 @@ static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) ...@@ -287,7 +287,7 @@ static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
if (DBG_USE_CPU_RELOC) if (DBG_USE_CPU_RELOC)
return DBG_USE_CPU_RELOC > 0; return DBG_USE_CPU_RELOC > 0;
return (HAS_LLC(obj->base.dev) || return (HAS_LLC(to_i915(obj->base.dev)) ||
obj->base.write_domain == I915_GEM_DOMAIN_CPU || obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
obj->cache_level != I915_CACHE_NONE); obj->cache_level != I915_CACHE_NONE);
} }
...@@ -833,7 +833,7 @@ need_reloc_mappable(struct i915_vma *vma) ...@@ -833,7 +833,7 @@ need_reloc_mappable(struct i915_vma *vma)
return false; return false;
/* See also use_cpu_reloc() */ /* See also use_cpu_reloc() */
if (HAS_LLC(vma->obj->base.dev)) if (HAS_LLC(to_i915(vma->obj->base.dev)))
return false; return false;
if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
......
...@@ -596,7 +596,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev, ...@@ -596,7 +596,8 @@ _i915_gem_object_create_stolen(struct drm_device *dev,
obj->stolen = stolen; obj->stolen = stolen;
obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT; obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE; obj->cache_level = HAS_LLC(to_i915(dev)) ?
I915_CACHE_LLC : I915_CACHE_NONE;
if (i915_gem_object_pin_pages(obj)) if (i915_gem_object_pin_pages(obj))
goto cleanup; goto cleanup;
......
...@@ -753,12 +753,13 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = { ...@@ -753,12 +753,13 @@ static const struct drm_i915_gem_object_ops i915_gem_userptr_ops = {
int int
i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file) i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{ {
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_userptr *args = data; struct drm_i915_gem_userptr *args = data;
struct drm_i915_gem_object *obj; struct drm_i915_gem_object *obj;
int ret; int ret;
u32 handle; u32 handle;
if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) { if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {
/* We cannot support coherent userptr objects on hw without /* We cannot support coherent userptr objects on hw without
* LLC and broken snooping. * LLC and broken snooping.
*/ */
......
...@@ -1492,7 +1492,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, ...@@ -1492,7 +1492,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
} }
/* 4: Everything else */ /* 4: Everything else */
if (HAS_HW_CONTEXTS(dev)) if (HAS_HW_CONTEXTS(dev_priv))
error->ccid = I915_READ(CCID); error->ccid = I915_READ(CCID);
if (INTEL_INFO(dev)->gen >= 8) { if (INTEL_INFO(dev)->gen >= 8) {
......
...@@ -942,14 +942,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, ...@@ -942,14 +942,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
uint8_t *recv, int recv_size) uint8_t *recv, int recv_size)
{ {
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv =
struct drm_i915_private *dev_priv = to_i915(dev); to_i915(intel_dig_port->base.base.dev);
i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
uint32_t aux_clock_divider; uint32_t aux_clock_divider;
int i, ret, recv_bytes; int i, ret, recv_bytes;
uint32_t status; uint32_t status;
int try, clock = 0; int try, clock = 0;
bool has_aux_irq = HAS_AUX_IRQ(dev); bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
bool vdd; bool vdd;
pps_lock(intel_dp); pps_lock(intel_dp);
......
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