Commit 02d8091b authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson

arm64: dts: qcom: msm8994: Add a proper CPU map

Add a proper CPU map to enable the use of all 8 cores.
Signed-off-by: default avatarKonrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200623224813.297077-4-konradybcio@gmail.comSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent b0ad598f
...@@ -28,24 +28,116 @@ sleep_clk: sleep_clk { ...@@ -28,24 +28,116 @@ sleep_clk: sleep_clk {
}; };
cpus { cpus {
#address-cells = <1>; #address-cells = <2>;
#size-cells = <0>; #size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&L2_1>;
};
cpu-map { cpu-map {
cluster0 { cluster0 {
core0 { core0 {
cpu = <&CPU0>; cpu = <&CPU0>;
}; };
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
}; };
};
CPU0: cpu@0 { cluster1 {
device_type = "cpu"; core0 {
compatible = "arm,cortex-a53"; cpu = <&CPU4>;
reg = <0x0>; };
next-level-cache = <&L2_0>;
L2_0: l2-cache { core1 {
compatible = "cache"; cpu = <&CPU5>;
cache-level = <2>; };
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
}; };
}; };
}; };
......
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